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KS57C0502/C0504/P0504 MICROCONTROLLER
PRODUCT OVERVIEW
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PRODUCT OVERVIEW
The KS57C0502/C0504 single-chip CMOS microcontroller has been designed for high-performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). The KS57P0504 is the microcontroller which has 4 Kbyte one-time-programmable ROM and the functions are the same to KS57C0502/C0504. With a four-channel comparator, eight LED direct drive pins, serial I/O interface, and its versatile 8-bit timer/counter, the KS57C0502/C0504 offers an excellent design solution for a wide variety of general-purpose applications. Up to 24 pins of the 30-pin SDIP package can be dedicated to I/O. Five vectored interrupts provide fast response to internal and external events. In addition, the KS57C0502/C0504's advanced CMOS technology provides for very low power consumption and a wide operating voltage range -- all at a very low cost.
FEATURES SUMMARY
MEMORY 512 x 4-bit data memory (RAM) 2048 x 8-bit program memory (ROM):KS57C0502 4096 x 8-bit program memory (ROM):KS57C0504 24 I/O PINS I/O: 18 pins, including 8 high current pins Input only: 6 pins COMPARATOR 4-channel mode: Internal reference (4-bit resolution) 16-step variable reference voltage 3-channel mode: External reference 150 mV resolution (worst case) 8-BIT BASIC TIMER Programmable interval timer Watch-dog timer 8-BIT TIMER/COUNTER Programmable interval timer External event counter function Timer/counter clock output to TCLO0 pin WATCH TIMER Time interval generation: 0.5 s, 3.9 ms at 4.19 MHz 4 frequency outputs to BUZ pin 8-BIT SERIAL I/O INTERFACE 8-bit transmit/receive mode 8-bit receive-only mode LSB-first or MSB-first transmission selectable Internal or external clock source BIT SEQUENTIAL CARRIER Supports 16-bit serial data transfer in arbitrary format INTERRUPTS Two external interrupt vectors Three internal interrupt vectors Two quasi-interrupts MEMORY-MAPPED I/O STRUCTURE Data memory bank 15 TWO POWER-DOWN MODES Idle mode: Only CPU clock stops Stop mode: System clock stops OSCILLATION SOURCES Crystal, Ceramic for system clock Crystal/ceramic: 0.4 - 6.0 MHz CPU clock divider circuit (by 4. 8, or 64) INSTRUCTION EXECUTION TIMES 0.95, 1.91, 15.3 s at 4.19 MHz 0.67, 1.33, 10.7 s at 6.0 MHz OPERATING TEMPERATURE - 40 C to 85 C OPERATING VOLTAGE RANGE 1.8 V to 5.5 V PACKAGE TYPE 30 SDIP, 32 SOP
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PRODUCT OVERVIEW
KS57C0502/C0504/P0504 MICROCONTROLLER
FUNCTION OVERVIEW
SAM47 CPU All KS57-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up to 32 K bytes of program memory. The arithmetic logic unit (ALU) performs 4-bit addition, subtraction, logical, and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two cycles. CPU REGISTERS Program Counter A 11-bit program counter (PC) stores addresses for instruction fetch during program execution. Usually, the PC is incremented by the number of bytes of the instruction being fetched. An exception is the 1-byte instruction REF which is used to reference instructions stored in a look-up table in the ROM. Whenever a reset operation or an interrupt occurs, bits PC11 through PC0 are set to the vector address. Bit PC13-12 is reserved to support future expansion of the device's ROM size. Stack Pointer An 8-bit stack pointer (SP) stores addresses for stack operations. The stack area is located in the generalpurpose data memory bank 0. The SP is read or written by 8-bit instructions and SP bit 0 must always be set to logic zero. During an interrupt or a subroutine call, the PC value and the PSW are saved to the stack area in RAM. When the service routine has completed, the values referenced by the stack pointer are restored. Then, the next instruction is executed. The stack pointer can access the stack regardless of data memory access enable flag status. Since the reset value of the stack pointer is not defined in firmware, it is recommended that the stack pointer be initialized to 00H by program code. This sets the first register of the stack area to data memory location 0FFH. PROGRAM MEMORY In its standard configuration, the 4096 x 8-bit ROM is divided into three functional areas: -- 16-byte area for vector addresses -- 96-byte instruction reference area -- 1920-byte general purpose area (KS57C0502) -- 3968-byte general purpose area (KS57C0504) The vector address area is used mostly during reset operations and interrupts. These 16 bytes can also be used as general-purpose ROM. The REF instruction references 2 x 1-byte and 2-byte instructions stored in locations 0020H-007FH. The REF instruction can also reference three-byte instructions such as JP or CALL. In order for REF to be able to reference these instructions, however, JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is is written to the reference area with the format TJP or TCALL instead of the normal instruction name. Unused locations in the instruction reference area can be allocated to general-purpose use.
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KS57C0502/C0504/P0504 MICROCONTROLLER
PRODUCT OVERVIEW
DATA MEMORY
Overview Data memory is organized into three areas: -- 32 x 4-bit working registers -- 224 x 4-bit general-purpose area in bank 0 -- 256 x 4-bit general-purpose area in bank 1 -- 128 x 4-bit area in bank 15 for memory-mapped I/O addresses Data stored in data memory can be manipulated by 1-, 4-, and 8-bit instructions. Data memory is organized into two memory banks -- bank 0, bank 1 and bank 15. The select memory bank instruction (SMB) selects the bank to be used as working data memory. After power-on reset operation, initialization values for data memory must be redefined by code. Data Memory Addressing Modes The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1 or 15. When the EMB flag is logic zero, restricted area can be accessed. When the EMB flag is set to logic one, all two data memory banks can be accessed according to the current SMB value. The EMB = "0" addressing mode is used for normal program execution, whereas the EMB = "1" mode is commonly used for interrupts, subroutines, mapped I/O, and repetitive access of specific RAM addresses. Working Registers The RAM's working register area in data memory bank 0 is further divided into four register banks. Each register bank has eight 4-bit registers that are addressable either by 1-bit or 4-bit instructions. Paired 4-bit registers can be addressed as double registers by 8-bit instructions. Register A is the 4-bit accumulator and double register EA is the 8-bit extended accumulator. Double registers WX, WL, and HL are used as data pointers for indirect addressing. Unused working registers can be used as general-purpose memory. To limit the possibility of data corruption due to incorrect register bank addressing, register bank 0 is usually used by the main program and banks 1, 2, and 3 for interrupt service routines.
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PRODUCT OVERVIEW
KS57C0502/C0504/P0504 MICROCONTROLLER
CONTROL REGISTERS
Program Status Word The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also used to restore a program's execution environment when an interrupt has been serviced. Program instructions can always address the PSW regardless of the current value of data memory enable flags. Before an interrupt or subroutine is processed, the PSW is pushed onto the stack in data memory bank 0. When the service routine is completed, the PSW values are restored. IS1 C IS0 SC2 EMB SC1 ERB SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the carry flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. You can address the skip condition flags (SC0-SC2) using 8-bit read instructions only. Select Bank (SB) Register Two 4-bit registers store address values used to access specific memory and register banks: the select memory bank register, SMB, and the select register bank register, SRB. 'SMB n' instruction selects a data memory bank (0 or 15) and stores the upper four bits of the 12-bit data memory address in the SMB register. To select register bank 0, 1, 2, or 3, and store the address data in the SRB, you use the instruction 'SRB n'. The instructions "PUSH SB" and "POP SB" move SRB and SMB values to and from the stack for interrupts and subroutines. CLOCK CIRCUITS System oscillation circuit generates the internal clock signals for the CPU and peripheral hardware. The system clock can use a crystal, or ceramic oscillation source, or an externally-generated clock signal. To drive KS57C0502/C0504 using an external clock source, the external clock signal should be input to Xin, and its inverted signal to Xout. 4-bit power control register controls the oscillation on/off, and select the CPU clock. The internal system clock signal (fx) can be divided internally to produce three CPU clock frequencies -- fx/4, fx/8, or fx/64. INTERRUPTS Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, and INTS) or externally by peripheral devices (INT0 and INT1). There are two quasi-interrupts: INTK and INTW. INTK (KS0-KS2) detects falling edges of incoming signals and INTW detects time intervals of 0.5 seconds or 3.91 milliseconds. The following components support interrupt processing: -- Interrupt enable flags -- Interrupt request flags -- Interrupt priority registers -- Power-down termination circuit
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KS57C0502/C0504/P0504 MICROCONTROLLER
PRODUCT OVERVIEW
POWER-DOWN To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates idle mode; the STOP instruction initiates stop mode. In idle mode, the CPU clock stops while peripherals continue to operate normally. In stop mode, system clock oscillation stops completely, halting all operations except for a few basic peripheral functions. A power-down is terminated either by a RESET or by an interrupt (with exception of the external interrupt INT0).
RESET
When RESET is input during normal operation or during power-down mode, a reset operation is initiated and the CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has elapsed, normal CPU operation resumes. I/O PORTS The KS57C0502/C0504 has seven I/O ports. Pin addresses for all I/O ports are mapped to locations FF0H- FF6H in bank 15 of the RAM. There are 6 input pins and 18 configurable I/O pins including 8 high current I/O pins for a total of 24 I/O pins. The contents of I/O port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. TIMERS and TIMER/COUNTER The timer function has three main components: an 8-bit basic timer, an 8-bit timer/counter, and a watch timer. The 8-bit basic timer generates interrupt requests at precise intervals, based on the selected internal clock frequency. The programmable 8-bit timer/counter is used for counting events, modifying internal clock frequencies, and dividing external clock signals. The 8-bit timer/counter generates a clock signal (SCK) for the serial I/O interface. The watch timer consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. Its functions include real-time, watch-time measurement, and clock generation for frequency output for buzzer sound. SERIAL I/O INTERFACE The serial I/O interface supports the transmission or reception of 8-bit serial data with an external device. The serial interface has the following functional components: -- 8-bit mode register -- Clock selector circuit -- 8-bit buffer register -- 3-bit serial clock counter The serial I/O circuit can be set to transmit-and-receive, or to receive-only mode. MSB-first or LSB-first transmission is also selectable. The serial interface can operate with an internal or an external clock source, or using the clock signal generated by the 8-bit timer/counter. Transmission frequency can be modified by setting the appropriate bits in the SIO mode register.
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PRODUCT OVERVIEW
KS57C0502/C0504/P0504 MICROCONTROLLER
BIT SEQUENTIAL CARRIER The bit sequential carrier (BSC) is a 16-bit register that can be manipulated using 1-, 4-, and 8-bit instructions. Using 1-bit indirect addressing, addresses and bit locations can be specified sequentially. In this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value of the L register. BSC data can also be manipulated using direct addressing. COMPARATOR The KS57C0502/C0504 contains a 4-channel comparator which can be multiplexed to normal input port. -- Conversion time: 15.2 s, 121.6 s at 4.19 MHz -- Two operation modes: Three channels for analog input and one channel for external reference voltage input Four channels for analog input and internal reference voltage level -- 16-level internal reference voltage generator -- 150 mV accuracy for input voltage level difference detection (maximum) -- Comparator enable and disable The comparison results are read from the 4-bit CMPREG register after the specified conversion time.
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KS57C0502/C0504/P0504 MICROCONTROLLER
PRODUCT OVERVIEW
BLOCK DIAGRAM
BASIC TIMER
WATCH TIMER
RESET
Xin
Xout P0.0 / SCK P0.1 / SO P0.2 / SI
8-BIT TIMER/ COUNTER
I/O PORT 0 INTERRUPT CONTROL BLOCK CLOCK STACK POINTER
P3.0 / TCL0 P3.1 / TCLO0 P3.2 / CLO
I/O PORT 3 INTERNAL INTERRUPTS
PROGRAM COUNTER
SERIAL I/O PORT
P4.0-P4.3
I/O PORT 4 INSTRUCTION DECODER
PROGRAM STATUS WORD
INPUT PORT 1
P1.0 / INT0 P1.1 / INT1 P2.0 / CIN0 P2.1 / CIN1 P2.2 / CIN2 P2.3 / CIN3
P5.0-P5.3
I/O PORT 5 ARITHMETIC LOGIC UNIT I/O PORT 6
INPUT PORT 2 FLAGS
COMPARATOR
P6.0 / KS0 P6.1 / KS1 P6.2 / KS2 P6.3 / BUZ
512 x 4-BIT DATA MEMORY
PROGRAM MEMORY KS57C0502: 2 KBYTE KS57C0504: 4 KBYTE
Figure 1-1. KS57C0502/C0504 Simplified Block Diagram
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PRODUCT OVERVIEW
KS57C0502/C0504/P0504 MICROCONTROLLER
PIN ASSIGNMENTS
VSS Xout Xin TEST P1.0 / INT0 P1.1 / INT1
RESET
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25 24
VDD P6.3 / BUZ P6.2 / KS2 P6.1 / KS1 P6.0 / KS0 P5.3 P5.2 P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 P3.2 / CLO P3.1 / TCLO0
P0.0 / SCK P0.1 / SO P0.2 / SI P2.0 / CIN0 P2.1 / CIN1 P2.2 / CIN2 P2.3 / CIN3 P3.0 / TCL0
KS57C0502/0504 23 (Top View) 22
21 20 19 18 17 16
30-pin SDIP
VSS Xout Xin TEST P1.0 / INT0 P1.1 / INT1
RESET
1 2 3 4 5 6 7 8 9
32 31 30 29 28 27 26
VDD P6.3 / BUZ P6.2 / KS2 P6.1 / KS1 P6.0 / KS0 P5.3 P5.2 P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 NC P3.2 / CLO P3.1 / TCLO0
NC P0.0 / SCK P0.1 / SO P0.2 / SI P2.0 / CIN0 P2.1 / CIN1 P2.2 / CIN2 P2.3 / CIN3 P3.0 / TCL0
KS57C0502/0504 25 24 (Top View)
23 22 21 20 19 18 17
10 11 12 13 14 15 16
32-pin SOP
Figure 1-2. KS57C0502/C0504 Pin Assignment Diagram
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KS57C0502/C0504/P0504 MICROCONTROLLER
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-2. KS57C0502/C0504 Pin Descriptions Pin Name P0.0 P0.1 P0.2 Pin Type I/O Description 3-bit I/O port. 1-bit or 3-bit read/write and test is possible. Pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. Pins are individually configurable as input or output. 2-bit input port. 1-bit or 2-bit read and test is possible. Pull-up resistors are assignable by software. 4-bit input port. 1-bit or 4-bit read and test is possible. Same as port 0 Number 8(9) 9(10) 10(11) Share Pin
SCK
SO SI
P1.0 P1.1 P2.0-P2.3 P3.0 P3.1 P3.2 P4.0-P4.3 P5.0-P5.3
I I I/O
5(5) 6(6) 11-14 (12-15) 15(16) 16(17) 17(18)
INT0 INT1 CIN0-CIN3 TCL0 TCLO0 CLO --
I/O
18-21(20-23) 4-bit I/O ports. 1-, 4-, or 8-bit read/write and test is 22-25(24-27) possible. Pins are individually configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. The N-channel open-drain or push-pull output can be selected by software (1-bit unit) 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. Pins are individually configurable as input or output. External interrupts with detection of rising and falling edges External interrupts with detection of rising or falling edges 4-channel comparator input. CIN0-CIN2: comparator input only. CIN3: comparator input or external reference input Serial interface clock signal Serial data output Serial data input External clock input for timer/counter Timer/counter clock output CPU clock output 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at 4.19 MHz for buzzer sound 26(28) 27(29) 28(30) 29(31)
P6.0 P6.1 P6.2 P6.3
I/O
KS0 KS1 KS2 BUZ
INT0 INT1 CIN0-CIN3
I I I
5(5) 6(6) 11-14(12-15)
P1.0 P1.1 P2.0-P2.3
SCK
I/O I/O I/O I/O I/O I/O I/O
8(9)
P0.0 P0.1 P0.2 P3.0 P3.1 P3.2 P6.3
SO SI TCL0 TCLO0 CLO BUZ
9(10) 10(11) 15(16) 16(17) 17(18) 29(31)
NOTE: Pin numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP.
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PRODUCT OVERVIEW
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 1-2. KS57C0502/C0504 Pin Descriptions (Continued) Pin Name KS0-KS2 VDD VSS
RESET
Pin Type I/O -- -- I I --
Description Quasi-interrupt input with falling edge detection Main power supply Ground Reset signal Test signal input (must be connected to VSS) Crystal or ceramic oscillator signal for system clock
Number 26-28(28-30) 30(32) 1(1) 7(7) 4(4) 3,2(3,2)
Share Pin P6.0-P6.2 -- -- -- -- --
TEST Xin, Xout
NOTE: Pin numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP.
Table 1-3. Overview of KS57C0502/C0504 Pin Data SDIP Pin Numbers 1 2,3 4 5,6 7 8-10 11-14 15-17 18-21 22-25 26-29 30 VSS Xout, Xin TEST P1.0, P1.1
RESET
Pin Names
Share Pins INT0, INT1
SCK, SO, SI
I/O Type I I I I/O I I/O I/O I/O I/O
Reset Value Input Input Input Input Input Input Input
Circuit Type A-3 B D-1 F-1, F-2 (note) D-1 E E D-1
P0.0 - P0.2 P2.0 - P2.3 P3.0 - P3.2 P4.0 - P4.3 P5.0 - P5.3 P6.0 - P6.3 VDD
CIN0 - CIN3 TCL0, TCLO0, CLO KS0, KS1, KS2, BUZ
NOTE: I/O circuit type F-2 is implemented for P2.3 only.
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KS57C0502/C0504/P0504 MICROCONTROLLER
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
PULL-UP RESISTOR P-CHANNEL
IN IN N-CHANNEL SCHMITT TRIGGER
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
VDD
PULL-UP RESISTOR
VDD
P-CHANNEL
P-CHANNEL RESISTOR ENABLE
DATA OUT N-CHANNEL
IN SCHMITT TRIGGER
OUTPUT DISABLE
Figure 1-4. Pin Circuit Type A-3
Figure 1-6. Pin Circuit Type C
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PRODUCT OVERVIEW
KS57C0502/C0504/P0504 MICROCONTROLLER
VDD
PULL-UP RESISTOR RESISTOR ENABLE P-CHANNEL
DIGITAL INPUT
DATA OUTPUT DISABLE
CIRCUIT TYPE 4
I/O
ANALOG INPUT
SCHMITT TRIGER
Figure 1-7. Pin Circuit Type D-1
Figure 1-9. Pin Circuit Type F-1
VDD
PNE
VDD
PULL-UP RESISTOR
DIGITAL INPUT
DATA
P-CHANNEL I/O
PULL-UP RESISTOR ENABLE
ANALOG INPUT
OUTPUT DISABLE
N-CHANNEL
EXTERNAL V REF
Figure 1-8. Pin Circuit Type E
Figure 1-10. Pin Circuit Type F-2
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KS57C0502/C0504/P0504 MICROCONTROLLER
ADDRESS SPACES
2
ADDRESS SPACES
PROGRAM MEMORY (ROM)
OVERVIEW ROM maps for KS57C0502/C0504 devices are mask programmable at the factory. In its standard configuration, the device's 4096 x 8-bit program memory has three areas that are directly addressable by the program counter (PC): -- 16-byte area for vector addresses -- 16-byte general-purpose area -- 96-byte instruction reference area -- 1920-byte general-purpose area: KS57C0502 -- 3968-byte general-purpose area: KS57C0504
General-Purpose Memory Two program memory areas are allocated for general-purpose use: One area is 16 bytes in size and the other is 1920 bytes (KS57C0502) or 3968 bytes (KS57C0504). Vector Addresses You use the 16-byte vector address area to store the vector addresses required to execute system resets and interrupts. Start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (EMB) and enable register bank (ERB) flags that are used to set their initial value for the corresponding service routines. The 16-byte area can be used alternately as general-purpose ROM. REF Instructions Locations 0020H-007FH are used as a reference area (look-up table) for 1-byte REF instructions. Using REF instructions, you can reduce the byte size of instruction operands. REF can reference either one 2-byte or two 1byte instructions stored in the look-up table. Unused look-up table addresses can be used as general-purpose ROM. Table 2-1. Program Memory Address Ranges ROM Area Function Vector address area General-purpose program memory REF instruction look-up table area General-purpose program memory Address Ranges 0000H-000FH 0010H-001FH 0020H-007FH 0080H-07FFH 0080H-0FFFH Area Size (in Bytes) 16 16 96 1920 (KS57C0502) 3968 (KS57C0504)
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ADDRESS SPACES
KS57C0502/C0504/P0504 MICROCONTROLLER
GENERAL-PURPOSE MEMORY AREAS The 16-byte area at ROM locations 0010H-001FH and the 3968-byte area at ROM locations 0080H-0FFFH are used as general-purpose program memory. You can also use vacant locations in the vector address area and REF instruction look-up table areas as general-purpose program memory. But please be careful not to overwrite live data when writing programs that use special-purpose areas of the ROM. VECTOR ADDRESS AREA Use the 16-byte vector address area of the ROM to store the vector addresses for executing system resets and interrupts. The starting addresses of interrupt service routines are stored in this area, along with the enable memory bank (EMB) and enable register bank (ERB) flag values that are needed to set EMB and ERB's initial values for the service routines. A 16-byte vector address is organized as follows: EMB PC7 ERB PC6 0 PC5 0 PC4 PC11 PC3 PC10 PC2 PC9 PC1 PC8 PC0
To set up the vector address area for specific programs, you use the instruction VENTn. The programming tips on the next page explain how to do this.
0000H
000FH 0010H
VECTOR ADDRESS AREA (16 Bytes) GENERAL-PURPOSE AREA (16 Bytes)
7 0000H
6
5
4
3
2
1
0
RESET
001FH 0020H INSTRUCTION REFERENCE AREA (96 Bytes) 007FH 0080H
KS57C0502 (1,920 Bytes)
0002H
INTB
0004H
INT0
0006H
GENERAL-PURPOSE AREA
INT1
0008H
INTS
07FFH 0800H
KS57C0504 (3,968 Bytes)
000AH
GENERAL-PURPOSE AREA
INTT0
0FFFH
Figure 2-1. ROM Structure
Figure 2-2. Vector Address Map
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KS57C0502/C0504/P0504 MICROCONTROLLER
ADDRESS SPACES
+ PROGRAMMING TIP -- Defining Vectored Interrupt Areas
The following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory: 1. When all vector interrupts are used: ORG ; VENT0 VENT1 VENT2 VENT3 VENT4 VENT5 1,0,RESET 0,0,INTB 0,0,INT0 0,0,INT1 0,0,INTS 0,0,INTT0 ; ; ; ; ; ; EMB EMB EMB EMB EMB EMB 0000H 1, ERB 0, ERB 0, ERB 0, ERB 0, ERB 0, ERB 0; Jump to RESET address 0; Jump to INTB address 0; Jump to INT0 address 0; Jump to INT1 address 0; Jump to INTS address 0; Jump to INTT0 address
2. When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt locations must be skipped with the assembly instruction ORG so that jumps will address the correct locations: ORG ; VENT0 VENT1 ORG VENT3 VENT4 ; ORG 0010H ; INTT0 interrupt not used 3. If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not written by a ORG instruction as in Example 2, a CPU malfunction will occur: ORG ; VENT0 VENT1 VENT3 VENT4 VENT5 ; ORG ; General-purpose ROM area ; In this example, when an INTS interrupt is generated, the corresponding vector area is not VENT4 INTS, but VENT5 INTT0. This causes an INTS interrupt to jump incorrectly to the INTT0 address and causes a CPU malfunction to occur. 0010H 1,0,RESET 0,0,INTB 0,0,INT1 0,0,INTS 0,0,INTT0 ; ; ; ; ; EMB EMB EMB EMB EMB 0000H 1, ERB 0, ERB 0, ERB 0, ERB 0, ERB 0; Jump to RESET address 0; Jump to INTB address 0; Jump to INT0 address 0; Jump to INT1 address 0; Jump to INTS address 1,0,RESET 0,0,INTB 0006H 0,0,INT1 0,0,INTS ; ; ; ; ; 0000H EMB 1, ERB 0; Jump to RESET address EMB 0, ERB 0; Jump to INTB address INT0 interrupt not used EMB 0, ERB 0; Jump to INT1 address EMB 0, ERB 0; Jump to INTS address
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ADDRESS SPACES
KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION REFERENCE AREA Using 1-byte REF instructions, you can easily reference instructions with larger byte sizes that are stored in addresses 0020H-007FH of program memory. This 96-byte area is called the REF instruction reference area, or look-up table. Locations in the REF look-up table may contain two one-byte instructions, a single two-byte instruction, or three-byte instructions such as a JP or CALL. The starting address of the instruction you are referencing must always be an even number. To reference a JP or CALL instruction, it must be written to the reference area in a two-byte format: for JP, this format is TJP; for CALL, it is TCALL. In summary, there are three ways to the REF instruction: -- Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions, -- Branching to any location by referencing a branch instruction stored in the look-up table, -- Calling subroutines at any location by referencing a call instruction stored in the look-up table.
+ PROGRAMMING TIP -- Using the REF Look-Up Table
Here is one example of how to use the REF instruction look-up table: ORG ; JMAIN KEYCK WATCH INCHL TJP BTSF TCALL LD INCS * * * LD ORG NOP NOP * * * REF REF REF REF REF * * * 0020H MAIN KEYFG CLOCK @HL,A HL ; ; ; ; 0, MAIN 1, KEYFG CHECK 2, CALL CLOCK 3, (HL) A
ABC ; MAIN
EA,#00H 0080
;
47, EA #00H
KEYCK JMAIN WATCH INCHL ABC
; ; ; ; ; ;
BTSF KEYFG (1-byte instruction) KEYFG = 1, jump to MAIN (1-byte instruction) KEYFG = 0, CALL CLOCK (1-byte instruction) LD @HL,A INCS HL LD EA,#00H (1-byte instruction)
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KS57C0502/C0504/P0504 MICROCONTROLLER
ADDRESS SPACES
DATA MEMORY (RAM)
OVERVIEW In its standard configuration, the 512 x 4-bit data memory has five areas: -- 32 x 4-bit working register area -- 224 x 4-bit general-purpose area in bank 0 (also used as stack area) -- 256 x 4-bit general-purpose area in bank 1 -- 128 x 4-bit area for memory-mapped I/O addresses To simplify referencing, the data memory area has two memory banks -- bank 0, bank 1 and bank 15. You use the select memory bank instruction (SMB) to select the bank you want to use as working data memory. Data stored in RAM locations are 1-, 4-, and 8-bit addressable. Initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following RESET. When RESET signal is generated in power-down mode, the data memory contents are maintained.
000H 01FH 020H
WORKING REGISTERS (32 x 4 Bits) GENERAL-PURPOSE REGISTERS AND STACK AREA (224 x 4 Bits) BANK 0
0FFH 100H GENERAL-PURPOSE (256 x 4 Bits) 1FFH BANK 1
~ ~
F80H PERIPHRAL HARDWARE REGISTERS FFFH
~ ~
BANK 15
Figure 2-3. Data Memory (RAM) Map
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KS57C0502/C0504/P0504 MICROCONTROLLER
Memory Banks 0, 1 and 15 Bank 0 (000H-0FFH) The lowest 32 nibbles of bank 0 (000H-01FH) are used as working registers; the next 224 nibbles (020H-0FFH) can be used both as stack area and as general-purpose data memory. Use the stack area for implementing subroutine calls and returns, and for interrupt processing. This area is used as general-purpose data memory. The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed RAM locations for each peripheral hardware address are mapped into this area.
Bank 1 Bank 15
(100H-1FFH) (F80H-FFFH)
Data Memory Addressing Modes The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0 or 15. When the EMB flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. With direct addressing, you can access locations 000H-07FH of bank 0, bank 1 and bank 15. With indirect addressing, only bank 0 (000H-0FFH) can be accessed. When the EMB flag is set to logic one, all two data memory banks can be accessed according to the current SMB value. For 8-bit addressing, two 4-bit registers are addressed as a register pair. When using 8-bit instructions to address RAM locations, remember to use the even-numbered register address as the instruction operand. Working Registers The RAM working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and 3). Each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable. Register A is used as a 4-bit accumulator and register pair EA is an 8-bit extended accumulator. The carry flag bit can also be used as a 1-bit accumulator. Register pairs WX, WL, and HL are used as address pointers for indirect addressing. To limit the possibility of data corruption due to incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines. Bit Sequential Carrier (BSC) The bit sequential carrier (BSC) is a 16-bit general register mapped to RAM addresses FC0H-FC3H that can be manipulated by 1-, 4-, and 8-bit RAM control instructions. RESET clears all bit values to logic zero. You can specify addresses and bit locations sequentially using a 1-bit indirect addressing instruction. In this way, a program can process 16-bit data by moving the bit location sequentially, incrementing or decrementing the value of the L register. BSC data can also be manipulated by direct addressing. For 8-bit manipulations, you must address the upper and lower 8 bits separately.
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ADDRESS SPACES
Table 2-2. Data Memory Organization and Addressing Addresses 000H-01FH 020H-0FFH 100H-1FFH F80H-FFFH Register Areas Working registers Stack and general-purpose registers General-purpose registers I/O-mapped hardware registers 1 15 1 0, 1 1 15 Bank 0 EMB Value 0, 1 SMB Value 0
+ PROGRAMMING TIP -- Clearing Data Memory Banks 0 and 1
Clear bank 0 of the data memory area: RAMCLR BITS SMB LD LD LD INCS JR EMB 0 HL,#10H A,#0H @HL,A HL RMCL0
RMCL0 ;
;
RAM (010H-0FFH) clear
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WORKING REGISTERS Working registers, mapped to RAM address 000H-01FH in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. Unused registers may be used as general-purpose memory. Working register data can be manipulated as 1-bit units, 4bit units or, using paired registers, as 8-bit units.
000H 0001
A
E
002H L 003H H 004H X 005H DATA MEMORY 006H BANK 0 007H 008H A ... Y A ... Y 00FH 010H A ... Y 017H 018H A ... Y 01FH REGISTER BANK 1 REGISTER BANK 2 REGISTER BANK 3 W Z Y WORKING REGISTER BANK 0
Figure 2-4. Working Register Map
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ADDRESS SPACES
Working Register Banks For addressing purposes, the working register area is divided into four register banks -- bank 0, bank 1, bank 2, and bank 3. Any one of these banks can be selected as the working register bank by the register bank selection instruction (SRBn) and by setting the status of the register bank enable flag (ERB). Generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service routines. Following this convention helps to prevent possible data corruption during program execution due to contention in register bank addressing. Table 2-3. Working Register Organization and Addressing ERB Setting 3 0 1 0 0 2 0 0 SRB Settings 1 x 0 0 1 1
NOTE: 'x' means don't care.
Selected Register Bank 0 x 0 1 0 1 Always set to bank 0 Bank 0 Bank 1 Bank 2 Bank 3
Paired Working Registers Each of the register banks is subdivided into eight 4-bit registers. These registers are named Y, Z, W, X, H, L, E and A. You can manipulate them individually using 4-bit instructions, or as register pairs for 8-bit data manipulation. The names of the 8-bit register pairs in each register bank are EA, HL, WX, YZ and WL. Registers A, L, X and Z always become the lower nibble when registers are addressed as 8-bit pairs. This makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks.
(MSB) Y
(LSB)
(MSB) Z
(LSB)
W
X
H
L
E
A
Figure 2-5. Register Pair Configuration
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Special-Purpose Working Registers You use register A as a 4-bit accumulator and double register EA as an 8-bit accumulator. You can use the carry flag as a 1-bit accumulator. 8-bit double registers WX, WL and HL are used as data pointers for indirect addressing. When the HL register serves as a data pointer, the instructions LDI, LDD, XCHI, and XCHD can make very efficient use of working registers as program loop counters by letting you transfer a value and increment or decrement L register value using a single instruction.
C A
1-BIT ACCUMULATOR 4-BIT ACCUMULATOR 8-BIT ACCUMULATOR
EA
Figure 2-6. 1-Bit, 4-Bit, and 8-Bit Accumulator
Recommendation for Multiple Interrupt Processing If more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank. When the routines have executed successfully, you can restore the register contents from the stack to working memory using the POP instruction.
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+ PROGRAMMING TIP -- Selecting Your Working Register Area
The following examples show the correct programming method for selecting working register area: 1. When ERB = "0": VENT2 ; INT0 1,0,INT0 PUSH SRB PUSH PUSH PUSH PUSH SMB LD LD LD INCS LD LD POP POP POP POP POP IRET SB 2 HL WX YZ EA 0 EA,#00H 80H,EA HL,#40H HL WX,EA YZ,EA EA YZ WX HL SB ; ; ; ; ; ; ; EMB 1, ERB 0, Jump to INT0 address PUSH current SMB, SRB Non-essential instruction, since ERB = "0" PUSH HL register to stack PUSH WX register to stack PUSH YZ register to stack PUSH EA register to stack
; ; ; ; ;
POP EA register from stack POP YZ register from stack POP WX register from stack POP HL register from stack POP current SMB, SRB
The POP instructions execute alternately with the PUSH instructions. If an SMB ninstruction is used in an interrupt service routine, a PUSH and POP SB instruction must be used to store and restore the current SMB and SRB values, as shown in Example 2 below. 2. When ERB = "1": VENT2 ; INT0 1,1,INT0 PUSH SRB SMB LD LD LD INCS LD LD POP IRET SB 2 0 EA,#00H 80H,EA HL,#40H HL WX,EA YZ,EA SB ; ; ; EMB 1, ERB 1, Jump to INT0 address Store current SMB, SRB Select register bank 2
;
Restore SMB, SRB
;
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STACK OPERATIONS
STACK POINTER (SP) The stack pointer (SP) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. The SP is mapped to RAM addresses F80H-F81H, and can be read or written by 8-bit control instructions. When addressing the SP, bit 0 must always remain cleared to logic zero. F80H F81H SP3 SP7 SP2 SP6 SP1 SP5 "0" SP4
There are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). A push decrements the SP and a pop increments it so that the SP always points to the top address of the last data to be written to the stack. The program counter contents and program status word are stored in the stack area prior to the execution of a CALL or a PUSH instruction, or during interrupt service routines. Stack operation is a LIFO (Last In-First Out) type. The stack area is located in general-purpose data memory bank 0. During an interrupt or a subroutine, the PC value and the PSW are saved to the stack area. When the routine has completed, the stack pointer is referenced to restore the PC and PSW, and the next instruction is executed. The SP can address stack registers in bank 0 (addresses 000H-0FFH) regardless of the current value of the enable memory bank (EMB) flag and the select memory bank (SMB) flag. Since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00H. This sets the first register of the stack area to 0FFH. NOTE A subroutine call occupies six nibbles in the stack; an interrupt requires six. When subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. To do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly. Although you may use general-purpose register areas for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s).
+ PROGRAMMING TIP -- Initializing the Stack Pointer
To initialize the stack pointer (SP): 1. When EMB = "1": SMB LD LD 2. When EMB = "0": LD LD EA,#00H SP,EA ; Memory addressing area (00H-7FH, F80H-FFFH) 15 EA,#00H SP,EA ; ; ; Select memory bank 15 Bit 0 of accumulator A is always cleared to "0" Stack area initial address (0FFH) (SP) - 1
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PUSH OPERATIONS Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the stack: PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decremented by a number determined by the type of push operation and then points to the next available stack location. PUSH Instructions A PUSH instruction references the SP to write two 4-bit data nibbles from the PC to the stack. Two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and another for the lower register. After the PUSH has executed, the SP is decremented by two and points to the next available stack location. CALL Instructions When a subroutine call is issued, the CALL instruction references the SP to write the PC's contents to four 4-bit stack locations. Current values for the enable memory bank (EMB) flag and the enable register bank (ERB) flag are also pushed to the stack. After the CALL has executed, the SP is decremented by six and points to the next available stack location. Since six 4-bit stack locations are used per CALL, you may nest subroutine calls up to the number of levels permitted in the stack. Interrupt Routines An interrupt routine references the SP to push the contents of the PC, as well as current values for the program status word (PSW) to the stack. Six 4-bit stack locations are used to store this data. After the interrupt has executed, the SP is decremented by six and points to the next available stack location. During an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area.
PUSH
(After PUSH, SP SP - 2) SP - 6 SP - 5 SP - 4 SP - 3 SP - 2 SP - 1 SP LOWER REGISTER UPPER REGISTER SP - 2 SP - 1 SP 0 0 0
CALL
(After CALL, SP PC 11-PC 8 0 0 0 SP - 6) SP - 6 SP - 5 SP - 4 SP - 3 SP - 2 SP - 1 SP
INTERRUPT
(When INT is acknowledged, SP SP - 6) PC 11-PC 8 0 0 0 0
PC3 - PC0 PC7 - PC4 0 0 EMB ERB 0 0
PC3 - PC0 PC7 - PC4 IS1 C IS0 EMB PSW SC2 SC1 ERB SC0
Figure 2-7. Push-Type Stack Operations
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POP OPERATIONS For each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction RET or SRET; for interrupts, the instruction IRET. When a pop operation occurs, the SP is incremented by a number determined by the type of operation and points to the next free stack location. POP Instructions A POP instruction references the SP to write data stored in two 4-bit stack locations back to the register pairs and SB register. The value for the lower 4-bit register is popped first, followed by the value for the upper 4-bit register. After the POP has executed, the SP is incremented by two and points to the next free stack location. RET and SRET Instructions The end of a subroutine call is signaled by the return instruction, RET or SRET. The RET or SRET uses the SP to reference the four 4-bit stack locations used for the CALL and to write this data back to the PC, the EMB, and ERB. After the RET or SRET has executed, the SP is incremented by six and points to the next free stack location. IRET Instructions The end of an interrupt sequence is signaled by the instruction IRET. IRET references the SP to locate the six 4-bit stack addresses used for the interrupt and to write this data back to the PC and the PSW. After the IRET has executed, the SP is incremented by six and points to the next free stack location.
POP
(SP SP SP + 1 SP + 2 SP + 2) SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 0 0 0 LOWER REGISTER UPPER REGISTER
RET OR SRET
(SP SP + 6) PC11-PC8 0 0 0 SP SP + 1 SP + 2 SP + 3 ERB 0 SP + 4 SP + 5 SP + 6 IS1 C 0 (SP
IRET
SP + 6) PC11-PC8 0 0 0
PC3 - PC0 PC7 - PC4 0 0 EMB 0
PC3 - PC0 PC7 - PC4 IS0 EMB ERB PSW SC2 SC1 SC0
Figure 2-8. Pop-Type Stack Operations
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BIT SEQUENTIAL CARRIER (BSC)
The bit sequential carrier (BSC) is a 16-bit register that is mapped to RAM addresses FC0H-FC3H. You can manipulate the BSC register using 1-, 4-, and 8-bit RAM control instructions. RESET clears all BSC bit values to logic zero. Using the BSC, you can specify addresses and bit locations sequentially using 1-bit indirect addressing (memb.@L). Bit addressing is independent of the current EMB value. In this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value of the L register. BSC data can also be manipulated using direct addressing. For 8-bit manipulations, specify the 4-bit register names BSC0 and BSC2 and manipulate the upper and lower 8 bits manipulated separately. If the values of the L register are 0H at BSC0.@L, the address and bit location assignment is FC0H.0. If the L register content is FH at BSC0.@L, the address and bit location assignment is FC3H.3. Table 2-4. BSC Register Organization Name BSC0 BSC1 BSC2 BSC3 Address FC0H FC1H FC2H FC3H Bit 3 BSC0.3 BSC1.3 BSC2.3 BSC3.3 Bit 2 BSC0.2 BSC1.2 BSC2.2 BSC3.2 Bit 1 BSC0.1 BSC1.1 BSC2.1 BSC3.1 Bit 0 BSC0.0 BSC1.0 BSC2.0 BSC3.0
+ PROGRAMMING TIP -- Using the BSC Register to Output 16-Bit Data
To use the bit sequential carrier (BSC) register to output 16-bit data (5937H) to the P3.0 pin: BITS SMB LD LD LD LD SMB LD LDB LDB INCS JR RET EMB 15 EA,#37H BSC0,EA EA,#59H BSC2,EA 0 L,#0H C,BSC0.@L P3.0,C L AGN
; ; ; ; ; ; ;
BSC0 A, BSC1 E BSC2 A, BSC3 E
AGN
P3.0 C
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PROGRAM COUNTER (PC)
A 12-bit program counter (PC) stores addresses for instruction fetches during program execution. Whenever a
reset operationor an interrupt occurs, bits PC11 through PC0 are set to the vector address. Bit PC12-PC13 is re-
served to support future expansion of the device's ROM size. Usually, the PC is incremented by the number of bytes of the instruction being fetched. One exception is the 1-byte REF instruction which is used to reference instructions stored in the ROM.
PROGRAM STATUS WORD (PSW)
The program status word (PSW) is an 8-bit word, mapped to RAM locations FB0H-FB1H, that defines system status and program execution status and which permits an interrupted process to resume operation after an interrupt request has been serviced. PSW values are mapped as follows: FB0H FB1H IS1 C IS0 SC2 EMB SC1 ERB SC0
The PSW can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the specific bit or bits being addressed. The PSW can be addressed during program execution regardless of the current value of the enable memory bank (EMB) flag. Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt. After the interrupt has been processed, the PSW values are popped from the stack back to the PSW address. When a RESET is generated, the EMB and ERB values are set according to the RESET vector address, and the carry flag is left undefined (or the current value is retained). PSW bits IS0, IS1, SC0, SC1, and SC2 are all cleared to logic zero. Table 2-5. Program Status Word Bit Descriptions PSW Bit Identifier IS1, IS0 EMB ERB C SC2, SC1, SC0 Description Interrupt status flags Enable memory bank flag Enable register bank flag Carry flag Program skip flags Bit Addressing 1, 4 1 1 1 8 Read/Write R/W R/W R/W R/W R
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INTERRUPT STATUS FLAGS (IS0, IS1) PSW bits IS0 and IS1 contain the current interrupt execution status values. They are mapped to RAM bit locations FB0H.2 and FB0H.3, respectively. You can manipulate IS0 and IS1 flags directly using 1-bit RAM control instructions By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. The interrupt priority control circuit determines the IS0 and IS1 settings in order to control multiple interrupt processing. When both interrupt status flags are set to "0", all interrupts are allowed. The priority with which interrupts are processed is then determined by the IPR. When an interrupt occurs, IS0 and IS1 are pushed to the stack as part of the PSW and are automatically incremented to the next higher priority level. Then, when the interrupt service routine ends with an IRET instruction, IS0 and IS1 values are restored to the PSW. Table 2-6 shows the effects of IS0 and IS1 flag settings. Table 2-6. Interrupt Status Flag Bit Settings IS1 Value 0 0 1 1 IS0 Value 0 1 0 1 Status of Currently Executing Process 0 1 2 -- Effect of IS0 and IS1 Settings on Interrupt Request Control All interrupt requests are serviced Only high-priority interrupt(s) as determined in the interrupt priority register (IPR) are serviced No more interrupt requests are serviced Not applicable; these bit settings are undefined
Since interrupt status flags can be addressed by write instructions, programs can exert direct control over interrupt processing status. Before interrupt status flags can be addressed, however, you must first execute a DI instruction to inhibit additional interrupt routines. When the bit manipulation has been completed, execute an EI instruction to re-enable interrupt processing.
+ PROGRAMMING TIP -- Setting ISx Flags for Interrupt Processing
The following instruction sequence shows how to use the IS0 and IS1 flags to control interrupt processing: INTB DI BITR IS1 BITS IS0 EI ; ; ; ; Disable interrupt IS1 0 Allow interrupts according to IPR priority level Enable interrupt
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EMB FLAG (EMB) The enable memory bank flag EMB is mapped to registers FB0H-FB1H in bank 15 of the RAM. The EMB flag occupies bit location 1 in register FB0H. The EMB flag is used to allocate specific address locations in the RAM by modifying the upper 4 bits of 12-bit data memory addresses. In this way, it controls the addressing mode for data memory banks 0, bank 1 or 15. When the EMB flag is "0", the data memory address space is restricted to bank 15 and addresses 000H-07FH of memory bank 0, regardless of the SMB register contents. When the EMB flag is set to "1", you can access general-purpose areas of bank 0, bank 1, and bank 15 by using the appropriate SMB value.
+ PROGRAMMING TIP -- Using the EMB Flag to Select Memory Banks
EMB flag settings for memory bank selection: 1. When EMB = "0": SMB LD LD SMB LD LD ; 2. When EMB = "1": SMB LD LD SMB LD LD ; 0 90H,A 34H,A 15 20H,A 90H,A ; ; ; ; ; ; Select memory bank 0 (090H) A, bank 0 is selected (034H) A, bank 0 is selected Select memory bank 15 Program error, but assembler does not detect it (F90H) A, bank 15 is selected 0 90H,A 34H,A 15 20H,A 90H,A ; ; ; ; ; ; Non-essential instruction, since EMB = "0" (F90H) A, bank 15 is selected (034H) A, bank 0 is selected Non-essential instruction, since EMB = "0" (020H) A, bank 0 is selected (F90H) A, bank 15 is selected
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ERB FLAG (ERB) The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the ERB flag is "1", you select the working register area from register banks 0 to 3 according to the register bank selection register (SRB). When the ERB flag is "0", you select register bank 0 as the working register area, regardless of the current value of the register bank selection register (SRB). When an internal RESET is generated, bit 6 of program memory address 0000H is written to the ERB flag. This automatically initializes the flag. When a vectored interrupt is generated, bit 6 of the respective vector address table in program memory is written to the ERB flag, setting the correct flag status before the interrupt service routine is executed. During the interrupt routine, the ERB value is automatically pushed to the stack area along with the other PSW bits. Afterwards, it is popped back to the FB0H.0 bit location. The initial ERB flag settings for each vectored interrupt are defined using VENTn instructions.
+ PROGRAMMING TIP -- Using the ERB Flag to Select Register Banks
ERB flag settings for register bank selection: 1. When ERB = "0": SRB LD LD SRB LD SRB LD ; 2. When ERB = "1": SRB LD LD SRB LD SRB LD ; 1 EA,#34H HL,EA 2 YZ,EA 3 WX,EA ; ; ; ; ; ; ; Register bank 1 is selected Bank 1 EA #34H Bank 1 HL Bank 1 EA Register bank 2 is selected Bank 2 YZ BANK 2 EA Register bank 3 is selected Bank 3 WX Bank 3 EA 1 EA,#34H HL,EA 2 YZ,EA 3 WX,EA ; ; ; ; ; ; ; ; Register bank 0 is selected (since ERB = "0", the SRB is configured to bank 0) Bank 0 EA #34H Bank 0 HL EA Register bank 0 is selected Bank 0 YZ EA Register bank 0 is selected Bank 0 WX EA
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SKIP CONDITION FLAGS (SC2, SC1, SC0) The skip condition flags SC2, SC1, and SC0 indicate the current program skip conditions and are set and reset automatically during program execution. These flags are mapped to RAM bit locations FB1H.0, FB1H.1, and FB1H.2 of the PSW. Skip condition flags can only be addressed by 8-bit read instructions. Direct manipulation of the SC2, SC1, and SC0 bits is not allowed. CARRY FLAG (C) The carry flag is mapped to bit location FB1H.3 in the PSW. It is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (ADC, SBC). The carry flag can also be used as a 1-bit accumulator for performing Boolean operations involving bit-addressed data memory. If an overflow or borrow condition occurs when executing arithmetic instructions with carry (ADC, SBC), the carry flag is set to "1". Otherwise, its value is "0". When a RESET occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined. The carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the PSW. Only the ADC and SBC instructions, and the instructions listed in Table 2-7, affect the carry flag. Table 2-7. Valid Carry Flag Manipulation Instructions Operation Type Direct manipulation SCF RCF CCF BTST C Bit transfer LDB (operand) (1),C LDB C,(operand) (1) Data transfer Boolean manipulation RRC A BAND C,(operand) (1) BOR C,(operand) (1) BXOR C,(operand) (1) Interrupt routine Return from interrupt INTn (2) IRET Instructions Carry Flag Manipulation Set carry flag to "1" Clear carry flag to "0" (reset carry flag) Invert carry flag value (complement carry flag) Test carry and skip if C = "1" Load carry flag value to the specified bit Load contents of the specified bit to carry flag Rotate right with carry flag AND the specified bit with contents of carry flag and save the result to the carry flag OR the specified bit with contents of carry flag and save the result to the carry flag XOR the specified bit with contents of carry flag and save the result to the carry flag Save carry flag to stack with other PSW bits Restore carry flag from stack with other PSW bits
NOTES: 1. The operand has three bit addressing formats: mema.a, memb.@L, and @H + DA.b. 2. INTn refers to the specific interrupt being executed and is not an instruction.
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+ PROGRAMMING TIP -- Using the Carry Flag as a 1-Bit Accumulator
1. Set the carry flag to logic one: SCF LD LD ADC ; ; ; ; C 1 EA #0C3H HL #0AAH EA #0C3H + #0AAH + #1H, C 1 EA,#0C3H HL,#0AAH EA,HL
2. Logical-AND bit 3 of address 3FH with P3.3 and output the result to P5.0: LD LDB BAND LDB H,#3H C,@H+0FH.3 C,P3.3 P5.0,C ; ; ; ; Set the upper four bits of the address to the H register value C bit 3 of 3FH C C AND P3.3 Output result from carry flag to P5.0
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NOTES
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ADDRESSING MODES
3
ADDRESSING MODES
OVERVIEW The enable memory bank flag, EMB, controls the two addressing modes for data memory. When you enable the EMB flag, you can address the entire RAM area. When you clear the EMB flag to logic zero, the addressable RAM is restricted to specific areas. The EMB flag works in connection with the select memory bank instruction, SMB n. You will recall that the SMB n instruction is used to select RAM bank 0, bank 1 or 15. The SMB setting is always contained in the upper four bits of a 12-bit RAM address. For this reason, both addressing modes (EMB = "0" and EMB = "1") apply specifically to the memory bank indicated by the SMB instruction, and any restrictions to the addressable area within banks 0, 1 or 15. Direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. In addition, there are several RAM locations that can always be addressed using specific addressing methods, regardless of the current EMB flag setting. Here are a few things to remember about addressing data memory areas: -- When you address peripheral hardware locations in bank 15, you can use the mnemonic for the memorymapped hardware component as the operand in place of the actual address location. -- Always use an even-numbered RAM address as the operand in 8-bit direct and indirect addressing. -- With direct addressing, use the RAM address as the instruction operand; with indirect addressing, the insttruction specifies a register which contains the operand's address.
3-1
ADDRESSING MODES
KS57C0502/C0504/P0504 MICROCONTROLLER
ADDRESSING MODE RAM AREAS 000H 01FH 020H 07FH 080H BANK 0 (GENERAL REGISTERS AND STACK) 0FFH 100H WORKING REGISTERS
DA DA.b EMB = 0 EMB = 1
@HL @H + DA.b EMB = 0 EMB = 1
@WX @WL X
mema.b X
memb.@L X
SMB = 0
SMB = 0
BANK 1: (GENERAL REGISTERS)
SMB = 1
SMB = 1
1FFH F80H BANK 15 (PERIPHERAL HARDWARE REGISTERS) FFFH NOTES: 1. 'X' means don't care. 2. Blank columns indicate RAM areas that are not addressable, given the addressing method and enable memory bank (EMB) flag setting shown in the column headers. FB0H FBFH FC0H FF0H
SMB = 15
SMB = 15
Figure 3-1. RAM Address Structure
3-2
KS57C0502/C0504/P0504 MICROCONTROLLER
ADDRESSING MODES
EMB AND ERB INITIALIZATION VALUES The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt vector address. When a RESET is generated internally, bit 7 of program memory address 0000H is written to the EMB flag, initializing it automatically. When a vectored interrupt is generated, bit 7 of the respective vector address table is written to the EMB. This automatically sets the EMB flag status for the interrupt service routine. When the interrupt is serviced, the EMB value is automatically saved to stack and then restored when the interrupt routine has completed. At the beginning of a program, the initial EMB flag value for each vectored interrupt must be set by using VENT instruction. The EMB can be set or reset by bit manipulation instructions (BITS, BITR) despite the current SMB setting.
+ PROGRAMMING TIP -- Initializing the EMB and ERB Flags
The following assembly instructions show how to initialize the EMB and ERB flag settings: ORG VENT0 VENT1 VENT2 VENT3 VENT4 VENT5 * * * BITR 0000H ; ROM address assignment
1,0,RESET ; EMB 1, ERB 0, branch RESET 0,1,INTB ; EMB 0, ERB 1, branch INTB 0,1,INT0 ; EMB 0, ERB 1, branch INT0 0,1,INT1 0,1,INTS 0,1,INTT0 ; EMB 0, ERB 1, branch INT1 ; EMB 0, ERB 1, branch INTS ; EMB 0, ERB 1, branch INTT0
RESET
EMB
3-3
ADDRESSING MODES
KS57C0502/C0504/P0504 MICROCONTROLLER
ENABLE MEMORY BANK SETTINGS
EMB = "1" When you set the enable memory bank flag, EMB, to logic one, you can address the data memory bank specified by the select memory bank (SMB) value (0,1 or 15) using 1-, 4-, or 8-bit instructions. You can use both direct and indirect addressing modes. The addressable RAM areas when the EMB flag is set to logic one are as follows: If SMB = 0, If SMB = 1 If SMB = 15, 000H-0FFH 100H-1FFH F80H-FFFH
EMB = "0" When the enable memory bank flag EMB is set to logic zero, the addressable area is defined independently of the SMB value, and is restricted to specific locations depending on whether a direct or indirect address mode is used. If EMB = "0", the addressable area is restricted to locations 000H-07FH in bank 0 and to locations F80H- FFFH in bank 15 for direct addressing. For indirect addressing, only locations 000H-0FFH in bank 0 are addressable, regardless of SMB value. To address the peripheral hardware register (bank 15) using indirect addressing, the EMB flag must first be set to "1" and the SMB value to "15". When a RESET occurs, the EMB flag is set to the value contained in bit 7 of ROM address 0000H. EMB-Independent Addressing You can address several areas of the data memory at any time, despite the status of the EMB flag. These exceptions are described in Table 3-1.
Table 3-1. RAM Addressing Not Affected by the EMB Value Address 000H-0FFH Addressing Method 4-bit indirect addressing using WX and WL register pairs; 8-bit indirect addressing using SP 1-bit direct addressing 1-bit indirect addressing using the L register Affected Hardware Not applicable LD PUSH POP PSW, IEx, IRQx, I/O BSC, I/O BITS BITR EMB IE1 Program Examples A,@WX
FB0H-FBFH FF0H-FFFH FC0H-FFFH
BTST FC3H.@L BAND C,P3.@L
3-4
KS57C0502/C0504/P0504 MICROCONTROLLER
ADDRESSING MODES
SELECT BANK REGISTER (SB) The select bank register (SB) is used to assign the memory bank and register bank. The 8-bit SB register consists of the 4-bit select register bank register (SRB) and the 4-bit select memory bank register (SMB), as shown in Figure 3-2.
SMB SB REGISTER SMB 3 SMB 2 SMB 1 SMB 0 0 0
SRB SRB 1 SRB 0
Figure 3-2. 4-Bit SMB and SRB Values in the SB Register During interrupts and subroutine calls, SB register contents can be saved to stack in 8-bit units by the PUSH SB instruction. You later restore the value to the SB using the POP SB instruction. Select Register Bank (SRB) Instruction The select register bank (SRB) value specifies which register bank is to be used as a working register bank. The SRB value is set by the 'SRB n' instruction, where n = 0, 1, 2, 3. One of the four register banks is selected by the combination of ERB flag status and the SRB value that you set using the 'SRB n' instruction. The current SRB value is retained until another register is requested by program software. PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts and subroutine calls. RESET clears the 4-bit SRB value to logic zero. Select Memory Bank (SMB) Instruction To select one of the two available data memory banks, you must execute an SMB n instruction specifying the number of the memory bank you want (0, 1 or 15). For example, the instruction 'SMB 1' selects bank 1 and 'SMB 15' selects bank 15. You must also remember to enable the memory bank you select by the appropriate enable memory bank flag (EMB) setting. The upper four bits of the 12-bit data memory address are stored in the SMB register. If the SMB value is not specified by software (or if a RESET does not occur) the current value is retained. RESET clears the 4-bit SMB value to logic zero. PUSH SB and POP SB instructions save and restore the contents of the SMB register to and from the stack area during interrupts and subroutine calls.
3-5
ADDRESSING MODES
KS57C0502/C0504/P0504 MICROCONTROLLER
DIRECT AND INDIRECT ADDRESSING You can directly address 1-bit, 4-bit, and 8-bit data stored in data memory locations using a specific register or bit address as the instruction operand. In indirect addressing the instruction specifies a specfic register pair which contain the address of the operand. The KS57 instruction set supports 1-bit, 4-bit, and 8-bit indirect addressing. For 8-bit indirect addressing, an even-numbered RAM address must always be used as the instruction operand, and the address register can be HL, WX, or WL of the selected register bank.
1-BIT ADDRESSING
Table 3-2. 1-Bit Direct and Indirect RAM Addressing Instruction Notation Addressing Mode Description EMB Flag Setting 0 Addressable Area 000H-07FH DA.b Direct: bit is indicated by the RAM address (DA), memory bank selection, and specified bit number (b). Direct: bit is indicated by addressable area (mema) and bit number (b). Indirect: lower two bits of register L as indicated by the upper 10 bits of RAM area (memb) and the upper two bits of register L. Indirect: bit indicated by the lower four bits of the address (DA), memory bank selection, and the H register identifier. F80H-FFFH Memory Bank Bank 0 Bank15 Hardware I/O Mapping -- All 1-bit addressable peripherals (SMB = 15) IS0, IS1, EMB, ERB, IEx, IRQx, Pn.n BSCn.x Pn.n
1 mema.b x
000H-FFFH FB0H-FBFH FF0H-FFFH FC0H-FFFH
SMB = 0, 1, 15 Bank 15
memb.@L
x
Bank 15
@H + DA.b
0
000H-0FFH
Bank 0
--
1
000H-FFFH
SMB = 0, 1, 15
All 1-bit addressable peripherals (SMB = 15)
NOTE: 'x' means don't care.
3-6
KS57C0502/C0504/P0504 MICROCONTROLLER
ADDRESSING MODES
+ PROGRAMMING TIP -- 1-Bit Addressing Modes
1-Bit Direct Addressing 1. If EMB = "0": AFLAG BFLAG CFLAG EQU EQU EQU SMB BITS BITS BTST BITS BITS 34H.3 85H.3 0BAH.0 0 AFLAG BFLAG CFLAG BFLAG P3.0
; ; ; ; ; ;
Non-essential instruction, since EMB = "0" 34H.3 1 F85H.3 (BMOD.3) 1 If FBAH.0 (IRQW) = 1, skip Else if FBAH.0 (IRQW) = 0, F85H.3 (BMOD.3) 1 FF3H.0 (P3.0) 1
; 2. If EMB = "1": AFLAG BFLAG CFLAG EQU EQU EQU SMB BITS BITS BTST BITS BITS 34H.3 85H.3 0BAH.0 0 AFLAG BFLAG CFLAG BFLAG P3.0
; ; ; ; ; ;
Select memory bank 0 34H.3 1 85H.3 1 If 0BAH.0 = 1, skip Else if 0BAH.0 = 0, 085H.3 1 FF3H.0 (P3.0) 1
;
3-7
ADDRESSING MODES
KS57C0502/C0504/P0504 MICROCONTROLLER
+ PROGRAMMING TIP -- 1-Bit Addressing Modes (Continued)
1-Bit Indirect Addressing 1. If EMB = "0": AFLAG BFLAG CFLAG EQU EQU EQU SMB LD BTSTZ BITS 34H.3 85H.3 0BAH.0 0 H,#0BH @H+CFLAG CFLAG
; ; ; ;
Non-essential instruction, since EMB = "0" H #0BH If 0BAH.0 = 1, 0BAH.0 0 and skip Else if 0BAH.0 = 0, FBAH.0 (IRQW) 1
; 2. If EMB = "1": AFLAG BFLAG CFLAG EQU EQU EQU SMB LD BTSTZ BITS 34H.3 85H.3 0BAH.0 0 H,#0BH @H+CFLAG CFLAG
; ; ; ;
Select memory bank 0 H #0BH If 0BAH.0 = 1, 0BAH.0 0 and skip Else if 0BAH.0 = 0, 0BAH.0 1
;
3-8
KS57C0502/C0504/P0504 MICROCONTROLLER
ADDRESSING MODES
4-BIT ADDRESSING Table 3-3. 4-Bit Direct and Indirect RAM Addressing Instruction Notation DA Addressing Mode Description Direct: 4-bit address indicated by the RAM address (DA) and the memory bank selection EMB Flag Setting 0 Addressable Area 000H-07FH F80H-FFFH Memory Bank Bank 0 Bank15 Hardware I/O Mapping -- All 4-bit addressable peripherals (SMB = 15) --
1 @HL Direct: 4-bit address indicated by the memory bank selection and register HL 0
000H-FFFH 000H-0FFH
SMB = 0, 1,15 Bank 0
1
000H-FFFH
SMB = 0, 15
@WX @WL
Indirect: 4-bit address indicated by register WX Indirect: 4-bit address indicated by register WL
x x
000H-0FFH 000H-0FFH
Bank 0 Bank 0
All 4-bit addressable peripherals (SMB = 15) --
NOTE: 'x' means don't care.
+ PROGRAMMING TIP -- 4-Bit Addressing Modes
4-Bit Direct Addressing 1. If EMB = "0": ADATA BDATA EQU EQU SMB LD SMB LD LD 46H 8EH 15 A,P3 0 ADATA,A BDATA,A
; ; ; ; ;
Non-essential instruction, since EMB = "0" A (P3) Non-essential instruction, since EMB = "0" (046H) A (F8EH) A
; 2. If EMB = "1": ADATA BDATA EQU EQU SMB LD SMB LD LD 46H 8EH 15 A,P3 0 ADATA,A BDATA,A
; ; ; ; ;
Select memory bank 15 A (P3) Select memory bank 0 (046H) A (08EH) A
;
3-9
ADDRESSING MODES
KS57C0502/C0504/P0504 MICROCONTROLLER
+ PROGRAMMING TIP -- 4-Bit Addressing Modes (Continued)
4-Bit Indirect Addressing 1. If EMB = "0", compare bank 0, locations 040H-046H with 060H-066H: ADATA BDATA EQU EQU SMB LD LD LD CPSE SRET DECS JR RET 46H 66H 15 HL,#BDATA WX,#ADATA A,@WL A,@HL L COMP
;
Non-essential instruction, since EMB = "0" A bank 0 (040H-046H) If bank 0 (060H-066H) = A, skip
COMP
; ;
; 2. If EMB = "1", exchange bank 0, 040H-046H with 060H-066H: ADATA BDATA EQU EQU SMB LD LD LD XCHD JR 46H 66H 0 HL,#BDATA WX,#ADATA A,@WL A,@HL TRANS
;
Select memory bank 0 A bank 0 (040H-046H) Bank 0 (060H-066H) A
TRANS
; ;
;
3-10
KS57C0502/C0504/P0504 MICROCONTROLLER
ADDRESSING MODES
8-BIT ADDRESSING
Table 3-4. 8-Bit Direct and Indirect RAM Addressing Instructio n Notation DA Addressing Mode Description EMB Flag Setting Addressable Area 000H-07FH Direct: 8-bit address indicated by the RAM address (DA = even number) and memory bank selection Indirect: the 8-bit address indicated by the memory bank selection and register HL; (the 4-bit L register value must be an even number) 0 F80H-FFFH Memory Bank Bank 0 Bank15 Hardware I/O Mapping -- All 8-bit addressable peripherals (SMB = 15) --
1 @HL 0
000H-FFFH 000H-0FFH
SMB = 0, 1, 15 Bank 0
1
000H-FFFH
SMB = 0, 1, 15
All 8-bit addressable peripherals (SMB = 15)
+ PROGRAMMING TIP -- 8-Bit Addressing Modes
8-Bit Direct Addressing: 1. If EMB = "0": ADATA BDATA EQU EQU SMB LD LD LD 46H 8EH 15 EA,P4 ADATA,EA BDATA,EA
; ; ; ;
Non-essential instruction, since EMB = "0" E (P5), A (P4) (046H) A, (047H) E (F8EH) A, (F8FH) E
; 2. If EMB = "1": ADATA BDATA EQU EQU SMB LD SMB LD LD 46H 8EH 15 EA,P4 0 ADATA,EA BDATA,EA
; ; ; ; ;
Select memory bank 15 E (P5), A (P4) Select memory bank 0 (046H) A, (047H) E (08EH) A, (08FH) E
;
3-11
ADDRESSING MODES
KS57C0502/C0504/P0504 MICROCONTROLLER
+ PROGRAMMING TIP -- 8-Bit Addressing Modes (Continued)
8-Bit Indirect Addressing 1. If EMB = "0": ADATA LD LD ; EQU 8EH HL,#ADATA EA,@HL
;
A (08EH), E (08FH)
2. If EMB = "1": ADATA SMB LD LD ; EQU 46H 0 HL,#ADATA EA,@HL
;
A (046H), E (047H)
3-12
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
4
MEMORY MAP
OVERVIEW To support program control of peripheral hardware, I/O addresses for peripherals are memory-mapped to bank 15 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. Access to bank 15 is controlled by the select memory bank (SMB) instruction and by the enable memory bank flag (EMB) setting.If the EMB flag is "0", bank 15 can be addressed using direct addressing, regardless of the current SMB value. You can use 1-bit direct and indirect addressing, however, for specific locations in bank 15, regardless of the current EMB value. I/O MAP FOR HARDWARE REGISTERS Table 4-1 contains detailed information about I/O mapping for peripheral hardware in bank 15 (register locations F80H-FFFH). Use the I/O map as a quick-reference source when writing application programs. The I/O map gives you the following information: -- Register address -- Register name (mnemonic for program addressing) -- Bit values (both addressable and non-manipulable) -- Read-only, write-only, or read and write addressability -- 1-bit, 4-bit, or 8-bit data manipulation characteristics
4-1
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 4-1. I/O Map for Memory Bank 15 Memory Bank 15 Address F80H F81H * * F85H F86H F87H F88H F89H * * F90H F91H F92H F93H F94H F95H F96H F97H F98H F99H F9AH * * FB0H FB1H FB2H FB3H FB4H FB5H FB6H FB7H IPR PCON IMOD0 IMOD1 IMODK PSW IS1 C (2) IME .3 .3 "0" "0" IS0 SC2 .2 .2 "0" "0" .2 EMB SC1 .1 .1 .1 "0" .1 ERB SC0 .0 .0 .0 .0 .0 R/W R W W W W W Yes No IME No No No No Yes No Yes Yes Yes Yes Yes No No No No No Yes WDTCF WDMOD .3 .7 .3 .2 .6 "0" .1 .5 "0" .0 .4 "0" W Yes No No W No No Yes TREF0 W No No Yes TCNT0 R No No Yes TMOD0 .3 "0" "0" .2 .6 TOE0 "0" .5 "0" "0" .4 "0" R/W Yes Yes No W .3 No Yes WMOD "0" .7 .2 "0" .1 .5 "0" (1) .4 W No No Yes BMOD BCNT .3 .2 .1 .0 W R .3 No Yes No No Yes Register SP Bit 3 .3 .7 Bit 2 .2 .6 Bit 1 .1 .5 Bit 0 "0" .4 R/W R/W Addressing Mode 1-Bit No 4-Bit No 8-Bit Yes
4-2
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
Table 4-1. I/O Map for Memory Bank 15 (Continued) Memory Bank 15 Address FB8H FB9H FBAH FBBH FBCH FBDH FBEH FBFH FC0H FC1H FC2H FC3H * * FD0H * * FD4H FD5H FD6H FD7H * * FDAH FDBH FDCH FDDH FDEH FDFH FE0H FE1H SMOD .3 .7 .2 .6 .1 .5 .0 "0" W .3 No Yes PUMOD PNE PNE4.3 PNE5.3 .3 "0" PNE4.2 PNE5.2 "0" .6 PNE4.1 PNE5.1 .1 .5 PNE4.0 PNE5.0 .0 .4 W No No Yes W No No Yes CMOD .3 .7 .2 .6 .1 .5 .0 "0" R/W No No Yes CMPREG R No Yes No CLMOD .3 "0" .1 .0 W No Yes No BSC0 BSC1 BSC2 BSC3 "0" "0" IE1 "0" "0" "0" IRQ1 "0" IET0 IES IE0 IEK IRQT0 IRQS IRQ0 IRQK R/W R/W R/W R/W Yes Yes Yes Yes Yes Yes Yes R/W Yes Yes No "0" "0" IEW IRQW R/W Yes Yes No Register Bit 3 "0" Bit 2 "0" Bit 1 IEB Bit 0 IRQB R/W R/W Addressing Mode 1-Bit Yes 4-Bit Yes 8-Bit No
4-3
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 4-1. I/O Map for Memory Bank 15 (Concluded) Memory Bank 15 Address FE2H FE3H FE4H FE5H FE6H FE7H FE8H FE9H FEAH FEBH FECH FEDH FEEH FEFH FF0H FF1H FF2H FF3H FF4H FF5H FF6H * * * FFFH
NOTES: 1. Bit 0 in the WMOD register must be set to logic "0". 2. The carry flag can be read or written by specific bit manipulation instructions only.
Addressing Mode Bit 1 .1 Bit 0 .0 R/W W R/W 1-Bit No No 4-Bit Yes No 8-Bit No Yes
Register P2MOD SBUF
Bit 3 .3
Bit 2 .2
PMG1 PMG2 PMG3
"0" "0" PM4.3 "0" PM5.3 PM6.3
PM0.2 PM3.2 PM4.2 "0" PM5.2 PM6.2
PM0.1 PM3.1 PM4.1 "0" PM5.1 PM6.1
PM0.0 PM3.0 PM4.0 "0" PM5.0 PM6.0
W W W
No No No
No No No
Yes Yes Yes
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6
-- -- .3 -- .3 .3 / .7 .3
.2 -- .2 .2 .2 .2 / .6 .2
.1 .1 .1 .1 .1 .1 / .5 .1
.0 .0 .0 .0 .0 .0 / .4 .0
R/W R R R/W R/W R/W R/W
Yes
Yes
No No No No Yes No
4-4
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
REGISTER DESCRIPTIONS In this section, register descriptions are presented in a consistent format to familiarize you with the memorymapped I/O locations in bank 15 of the RAM. Figure 4-1 describes features of the register description format. Register descriptions are arranged in alphabetical order. Counter registers, buffer registers, and reference registers, as well as the stack pointer and port I/O latches, are not included in these descriptions. This section can be used as a quick-reference source when writing application programs. More detailed information about each of these registers is included in Part II of this manual, "Hardware Descriptions," in the context of the corresponding peripheral hardware module descriptions.
4-5
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
Bit identifiers used for bit addressing Register ID
Name of individual bit or related bits Register name Register location in RAM bank 15
IPR -- Interrupt Priority Register Bit Identifier RESET Value Read/Write Bit Addressing 3 IME 0 W 1/4 2 .2 0 W 4 1 .1 0 W 4 0 .0 0 W 4
FB2H
IME
Global Interrupt Enable Bit 0 1 Disable interrupt processing globally Enable interrupt processing globally
.2 - .0
Interrupt Priority Assignment Bits 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 Process all interrupt requests at low priority Process I NTB interrupts only Process INT0 interrupts only Process INT1 interrupts only Process INTT interrupts only
R= W= R/W = '-' =
Read-only Write-only Read/write Not used Type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit)
Bit value immediately following a reset
Bit number in MSB to LSB order
Description of the effect of specific bit settings
Bit identifier used for bit addressing
Figure 4-1. Register Description Format
4-6
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
BMOD -- Basic Timer Mode Register
Bit Identifier
RESET Value
F85H
1 .1 0 W 4 0 .0 0 W 4
3 .3 0 W 1/4
2 .2 0 W 4
Read/Write Bit Addressing BMOD.3
Basic Timer Restart Bit 1 Restart basic timer, then clear IRQB flag, BCNT and BMOD.3 to logic zero
BMOD.2 - .0
Input Clock Frequency and Signal Stabilization Interval Control Bits 0 0 1 1 0 1 0 1 0 1 1 1 Input clock frequency: Signal stabilization interval: Input clock frequency: Signal stabilization interval: Input clock frequency: Signal stabilization interval: Input clock frequency: Signal stabilization interval: fx / 212 (1.02 kHz) 220 / fx (250 ms) fx / 29 (8.18 kHz) 217 / fx (31.3 ms) fx / 27 (32.7 kHz) 215 / fx (7.82 ms) fx / 25 (131 kHz) 213 / fx (1.95 ms)
NOTES: 1. Signal stabilization interval is the time required to stabilize clock signal oscillation after stop mode is terminated by an interrupt. 2. When a RESET occurs, the oscillation stabilization time is 31.3 ms at 4.19 MHz. 3. 'fx' is the system clock rate given a clock frequency of 4.19 MHz.
4-7
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
CMOD -- Comparator Mode Register
Bit Identifier
RESET Value
FD7H, FD6H
5 .5 0 4 "0" 0 R/W 8 3 .3 0 R/W 8 2 .2 0 R/W 8 1 .1 0 R/W 8 0 .0 0 R/W 8
7 .7 0 R/W 8
6 .6 0 R/W 8
Read/Write Bit Addressing CMOD.7
R/W 8
Comparator Enable/Disable Bit 1 0 Comparator operation enable Comparator operation disable
CMOD.5
External/Internal Reference Selection Bit 1 0 External reference at CIN3, CIN0-2: analog input Internal reference, CIN0-3: analog input
CMOD.6
Conversion Time Control Bit 1 0 4 x 24 / fx, 15.2 s @4.19 MHz 4 x 27 / fx, 121.6 s @4.19 MHz
CMOD.4
Bit 4 0 Always logic zero
CMOD.3 - .0
Reference Voltage Selection Bits Selected VREF VDD x (n + 0.5) 16 , n = 0 to 15
4-8
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
CLMOD -- Clock Output Mode Register
Bit Identifier
RESET Value
FD0H
0 .0 0 W 4
3 .3 0 W 4
2 "0" 0 W 4
1 .1 0 W 4
Read/Write Bit Addressing CLMOD.3
Enable/Disable Clock Output Control Bit 0 1 Disable clock output Enable clock output
CLMOD.2
Bit 2 0 Always logic zero
CLMOD.1 - .0
Clock Source and Frequency Selection Control Bits 0 0 1 1 0 1 0 1 Select CPU clock source fx/4, fx/8, or fx/64 (1.05 MHz, 524 kHz, or 65.6 kHz) Select system clock fx/8 (524 kHz) Select system clock fx/16 (262 kHz) Select system clock fx/64 (65.5 kHz)
NOTE: fx' is the system clock given a clock frequency of 4.19 MHz.
4-9
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
IE0, 1, IRQ0, 1 -- INT0, 1 Interrupt Enable/Request Flags
Bit Identifier
RESET Value
FBEH
3 IE1 0 R/W 1/4
2 IRQ1 0 R/W 1/4
1 IE0 0 R/W 1/4
0 IRQ0 0 R/W 1/4
Read/Write Bit Addressing IE1
INT1 Interrupt Enable Flag 0 1 Disable interrupt requests at the INT1 pin Enable interrupt requests at the INT1 pin
IRQ1
INT1 Interrupt Request Flag - Generate INT1 interrupt (bit is set and cleared by hardware when rising or falling edge detected at INT1 pin.)
IE0
INT0 Interrupt Enable Flag 0 1 Disable interrupt requests at the INT0 pin Enable interrupt requests at the INT0 pin
IRQ0
INT0 Interrupt Request Flag - Generate INT0 interrupt (bit is set and cleared by hardware when rising or falling edge detected at INT0 pin.)
4-10
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
IEK, IRQK -- Key Interrupt Enable/Request Register
Bit Identifier
RESET Value
FBFH
3 0 0 R/W 1/4 Bits 3-2 0
2 0 0 R/W 1/4
1 IEK 0 R/W 1/4
0 IRQK 0 R/W 1/4
Read/Write Bit Addressing .3 - .2
Always logic zero
IEK
Key Interrupt Request Enable Flag 0 1 Disable INTK interrupt requests at the KS0-KS2 pins Enable INTK interrupt requests at the KS0-KS2 pin
IRQK
Key Interrupt Request Flag - Generate INTK interrupt. (This bit is set when falling edge detected any at one of the KS0-KS2 pins. INTK is a quasi-interrupt and IRQK must be cleared by software.)
4-11
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
IEB, IRQB -- INTB Interrupt Enable/Request Flags
Bit Identifier
RESET Value
FB8H
3 0 0 R/W 1/4 Bits 3-2 0
2 0 0 R/W 1/4
1 IEB 0 R/W 1/4
0 IRQB 0 R/W 1/4
Read/Write Bit Addressing .3 - .2
Always logic zero
IEB
INTB Interrupt Enable Flag 0 1 Disable INTB interrupt requests Enable INTB interrupt requests
IRQB
INTB Interrupt Request Flag - Generate INTB interrupt (bit is set and cleared automatically by hardware when reference interval signal received from basic timer.)
4-12
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
IES, IRQS -- INTS Interrupt Enable/Request Flags
Bit Identifier
RESET Value
FBDH
3 0 0 R/W 1/4 Bits 3-2 0
2 0 0 R/W 1/4
1 IES 0 R/W 1/4
0 IRQS 0 R/W 1/4
Read/Write Bit Addressing .3 - .2
Always logic zero
IES
INTS Interrupt Enable Flag 0 1 Disable INTS interrupt requests Enable INTS interrupt requests
IRQS
INTS Interrupt Request Flag - Generate INTS interrupt (bit is set and cleared automatically by hardware when transmit or receive operation is completed.)
4-13
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
IET0, IRQT0 -- INTT0 Interrupt Enable/Request Flags
Bit Identifier
RESET Value
FBCH
3 0 0 R/W 1/4 Bits 3-2 0
2 0 0 R/W 1/4
1 IET0 0 R/W 1/4
0 IRQT0 0 R/W 1/4
Read/Write Bit Addressing .3 - .2
Always logic zero
IET0
INTT0 Interrupt Enable Flag 0 1 Disable INTT0 interrupt requests Enable INTT0 interrupt requests
IRQT0
INTT0 Interrupt Request Flag - Generate INTT0 interrupt (bit is set and cleared automatically by hardware when contents of TCNT0 and TREF0 registers match.)
4-14
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
IEW, IRQW -- INTW Interrupt Enable/Request Flags
Bit Identifier
RESET Value
FBAH
3 0 0 R/W 1/4 Bits 3-2 0
2 0 0 R/W 1/4
1 IEW 0 R/W 1/4
0 IRQW 0 R/W 1/4
Read/Write Bit Addressing .3 - .2
Always logic zero
IEW
INTW Interrupt Enable Flag 0 1 Disable INTW interrupt requests Enable INTW interrupt requests
IRQW
INTW Interrupt Request Flag - Generate INTW interrupt (bit is set when timer interval = 0.5 s or 3.19 ms)
NOTE: INTW is a quasi-interrupt and its request flag must be cleared by software.
4-15
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
IMOD0 -- External Interrupt 0 (INT0) Mode Register
Bit Identifier
RESET Value
FB4H
3 .3 0 W 4
2 "0" 0 W 4
1 .1 0 W 4
0 .0 0 W 4
Read/Write Bit Addressing IMOD0.3
Interrupt Sampling Clock Selection Bit 0 1 Select CPU clock as a sampling clock Select sampling clock frequency of the system clock (fx)/64
IMOD0.2
Bit 2 0 Always logic zero
IMOD0.1 - .0
External Interrupt Mode Control Bits 0 0 1 1 0 1 0 1 Interrupt requests are triggered by a rising signal edge Interrupt requests are triggered by a falling signal edge Interrupt requests are triggered by both rising and falling signal edges Interrupt request flag (IRQ0) cannot be set to logic one
4-16
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
IMOD1 -- External Interrupt 1 (INT1) Mode Register
Bit Identifier
RESET Value
FB5H
3 "0" 0 W 4 Bits 3-1 0
2 "0" 0 W 4
1 "0" 0 W 4
0 .0 0 W 4
Read/Write Bit Addressing IMOD1.3 - .1
Always logic zero
IMOD1.0
External Interrupt 1 Edge Detection Control Bit 0 1 Rising edge detection Falling edge detection
4-17
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
IMODK -- Key Interrupt Mode Register
Bit Identifier
RESET Value
FB6H
0 .0 0 W 4
3 "0" 0 W 4 Bits 3 0
2 .2 0 W 4
1 .1 0 W 4
Read/Write Bit Addressing IMODK.3
Always logic zero
IMODK.2 - .0
Key Interrupt Edge Detection Selection Bit 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Interrupt request is disabled Interrupt request at KS0 triggered by falling edge Interrupt request at KS1 triggered by falling edge Interrupt request at KS0-KS1 triggered by falling edge Interrupt request at KS2 triggered by falling edge Interrupt request at KS0, KS2 triggered by falling edge Interrupt request at KS1.-KS2 triggered by falling edge Interrupt request at KS0-KS2 triggered by falling edge
4-18
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
IPR -- Interrupt Priority Register
Bit Identifier
RESET Value
FB2H
1 .1 0 W 4 0 .0 0 W 4
3 IME 0 W 1/4
2 .2 0 W 4
Read/Write Bit Addressing IME
Interrupt Master Enable Bit 0 1 Inhibit all interrupt processing Enable processing for all interrupt service requests
IPR.2 - .0
Interrupt Priority Assignment Bits 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Process all interrupt requests at low priority Process INTB interrupt only Process INT0 interrupts only Process INT1 interrupts only Process INTS interrupts only Process INTT0 interrupts only
4-19
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
PCON -- Clock Power Control Register
Bit Identifier
RESET Value
FB3H
0 .0 0 W 4
3 .3 0 W 4
2 .2 0 W 4
1 .1 0 W 4
Read/Write Bit Addressing PCON.3 - .2
CPU Operating Mode Control Bits 0 0 1 0 1 0 Enable normal CPU operating mode Initiate idle power-down mode Initiate stop power-down mode
PCON.1 - .0
CPU Clock Frequency Selection Bits 0 1 1 0 0 1 Select (fx)/64 Select fx/8 Select fx/4
*
fx = system clock
4-20
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
PMG1 -- Port I/O Mode Flags (Group 1: Ports 0, 3)
Bit Identifier
RESET Value
FE9H, FE8H
3 "0" 0 W 8 2 PM0.2 0 W 8 1 PM0.1 0 W 8 0 PM0.0 0 W 8
7 "0" 0 W 8 Bit 7 0
6 PM3.2 0 W 8
5 PM3.1 0 W 8
4 PM3.0 0 W 8
Read/Write Bit Addressing .7
Always logic zero
PM3.2
P3.2 I/O Mode Selection Flag 0 1 Set P3.2 to input mode Set P3.2 to output mode
PM3.1
P3.1 I/O Mode Selection Flag 0 1 Set P3.1 to input mode Set P3.1 to output mode
PM3.0
P3.0 I/O Mode Selection Flag 0 1 Set P3.0 to input mode Set P3.0 to output mode
.4
Bit 4 0 Always logic zero
PM0.2
P0.2 I/O Mode Selection Flag 0 1 Set P0.2 to input mode Set P0.2 to output mode
PM0.1
P0.1 I/O Mode Selection Flag 0 1 Set P0.1 to input mode Set P0.1 to output mode
PM0.0
P0.0 I/O Mode Selection Flag 0 1 Set P0.0 to input mode Set P0.0 to output mode
4-21
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
PMG2 -- Port I/O Mode Flags (Group 2: Port 4)
Bit Identifier
RESET Value
FEBH, FEAH
3 PM4.3 0 W 8 2 PM4.2 0 W 8 1 PM4.1 0 W 8 0 PM4.0 0 W 8
7 "0" 0 W 8 Bit 7 0
6 "0" 0 W 8
5 "0" 0 W 8
4 "0" 0 W 8
Read/Write Bit Addressing .7
Always logic zero
.6
Bit 6 0 Always logic zero
.5
Bit 5 0 Always logic zero
.4
Bit 4 0 Always logic zero
PM4.3
P4.3 I/O Mode Selection Flag 0 1 Set P4.3 to input mode Set P4.3 to output mode
PM4.2
P4.2 I/O Mode Selection Flag 0 1 Set P4.2 to input mode Set P4.2 to output mode
PM4.1
P4.1 I/O Mode Selection Flag 0 1 Set P4.1 to input mode Set P4.1 to output mode
PM4.0
P4.0 I/O Mode Selection Flag 0 1 Set P4.0 to input mode Set P4.0 to output mode
4-22
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
PMG3 -- Port I/O Mode Flags (Group 3: Port 5, 6)
Bit Identifier
RESET Value
FEDH, FECH
3 PM5.3 0 W 8 2 PM5.2 0 W 8 1 PM5.1 0 W 8 0 PM5.0 0 W 8
7 PM6.3 0 W 8
6 PM6.2 0 W 8
5 PM6.1 0 W 8
4 PM6.0 0 W 8
Read/Write Bit Addressing PM6.3
P6.3 I/O Mode Selection Flag 0 1 Set P6.3 to input mode Set P6.3 to output mode
PM6.2
P6.2 I/O Mode Selection Flag 0 1 Set P6.2 to input mode Set P6.2 to output mode
PM6.1
P6.1 I/O Mode Selection Flag 0 1 Set P6.1 to input mode Set P6.1 to output mode
PM6.0
P6.0 I/O Mode Selection Flag 0 1 Set P6.0 to input mode Set P6.0 to output mode
PM5.3
P5.3 I/O Mode Selection Flag 0 1 Set P5.3 to input mode Set P5.3 to output mode
PM5.2
P5.2 I/O Mode Selection Flag 0 1 Set P5.2 to input mode Set P5.2 to output mode
PM5.1
P5.1 I/O Mode Selection Flag 0 1 Set P5.1 to input mode Set P5.1 to output mode
PM5.0
P5.0 I/O Mode Selection Flag 0 1 Set P5.0 to input mode Set P5.0 to output mode
4-23
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
PNE -- N-channel Open-drain Enable Register
Bit Identifier
RESET Value
FDAH
4 3 PNE4.3 0 W 8 2 PNE4.2 0 W 8 1 PNE4.1 0 W 8 0 PNE4.0 0 W 8
7 PNE5.3 0 W 8
6 PNE5.2 0 W 8
5 PNE5.1 0 W 8
PNE5.0 0 W 8
Read/Write Bit Addressing .7
P5.3 N-channel Open-drain Enable Bit 0 1 Set P5.3 Open-drain Disabled Set P5.3 Open-drain Enabled
.6
P5.2 N-channel Open-drain Enable Bit 0 1 Set P5.2 Open-drain Disabled Set P5.2 Open-drain Enabled
.5
P5.1 N-channel Open-drain Enable Bit 0 1 Set P5.1 Open-drain Disabled Set P5.1 Open-drain Enabled
.4
P5.0 N-channel Open-drain Enable Bit 0 1 Set P5.0 Open-drain Disabled Set P5.0 Open-drain Enabled
.3
P4.3 N-channel Open-drain Enable Bit 0 1 Set P4.3 Open-drain Disabled Set P4.3 Open-drain Enabled
.2
P4.2 N-channel Open-drain Enable Bit 0 1 Set P4.2 Open-drain Disabled Set P4.2 Open-drain Enabled
.1
P4.1 N-channel Open-drain Enable Bit 0 1 Set P4.1 Open-drain Disabled Set P4.1 Open-drain Enabled
.0
P4.0 N-channel Open-drain Enable Bit 0 1 Set P4.0 Open-drain Disabled Set P4.0 Open-drain Enabled
4-24
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
PSW -- Program Status Word
Bit Identifier
RESET Value
FB1H, FB0H
6 5 SC1 0 R 8 4 SC0 0 R 8 3 IS1 0 R/W 1/4 2 IS0 0 R/W 1/4 1 EMB 0 R/W 1 0 ERB 0 R/W 1
7 C
(NOTE 1)
SC2 0 R 8
Read/Write Bit Addressing C
R/W
(NOTE 2)
Carry Flag 0 1 No overflow or borrow condition exists An overflow or borrow condition does exist
SC2 - SC0
Skip Condition Flags 0 1 No skip condition exists; no direct manipulation of these bits is allowed A skip condition exists; no direct manipulation of these bits is allowed
IS1, IS0
Interrupt Status Flags 0 0 1 1 0 1 0 1 Service all interrupt requests Service only the high-priority interrupt(s) as determined in the interrupt priority register (IPR) Do not service any more interrupt requests Undefined
EMB
Enable Data Memory Bank Flag 0 1 Restrict program access to data memory to bank 15 (F80H-FFFH) and to the locations 000H-07FH in the bank 0 only Enable full access to data memory banks 0, 1, and 15
ERB
Enable Register Bank Flag 0 1 Select register bank 0 as working register area Select register banks 0, 1, 2, or 3 as working register area in accordance with the select register bank (SRB) instruction operand
NOTES: 1. The value of the carry flag after a RESET occurs during normal operation is undefined. If a RESET occurs during power-down mode (IDLE or STOP), the current value of the carry flag is retained. 2. The carry flag can only be addressed by a specific set of 1-bit manipulation instructions. See Section 2 for detailed information.
4-25
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
P2MOD -- Port 2 Mode Register
Bit Identifier
RESET Value
FE2H
1 .1 0 W 4 0 .0 0 W 4
3 .3 0 W 4
2 .2 0 W 4
Read/Write Bit Addressing P2MOD.3
P2.3 Analog/digital Selection Bit 0 1 Configure P2.3 as an analog input pin Configure P2.3 as an digital input pin
P2MOD.2
P2.2 Analog/digital Selection Bit 0 1 Configure P2.2 as an analog input pin Configure P2.2 as an digital input pin
P2MOD.1
P2.1 Analog/digital Selection Bit 0 1 Configure P2.1 as an analog input pin Configure P2.1 as an digital input pin
P2MOD.0
P2.0 Analog/digital Selection Bit 0 1 Configure P2.0 as an analog input pin Configure P2.0 as an digital input pin
4-26
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
PUMOD -- Pull-Up Register Mode Register
Bit Identifier
RESET Value
FDCH, FDDH
4 .4 0 W 8 3 .3 0 W 8 2 "0" 0 W 8 1 .1 0 W 8 0 .0 0 W 8
7 "0" 0 W 8 Bit 7 0
6 .6 0 W 8
5 .5 0 W 8
Read/Write Bit Addressing .7
Always cleared to logic zero
.6
Connect/Disconnect Port 6 Pull-Up Resistor Control Bit 0 1 Disconnect port 6 pull-up resistor Connect port 6 pull-up resistor
.5
Connect/Disconnect Port 5 Pull-Up Resistor Control Bit 0 1 Disconnect port 5 pull-up resistor Connect port 5 pull-up resistor
.4
Connect/Disconnect Port 4 Pull-Up Resistor Control Bit 0 1 Disconnect port 4 pull-up resistor Connect port 4 pull-up resistor
.3
Connect/Disconnect Port 3 Pull-Up Resistor Control Bit 0 1 Disconnect port 3 pull-up resistor Connect port 3 pull-up resistor
.2
Bit 2 0 Always cleared to logic zero
.1
Connect/Disconnect Port 1 Pull-Up Resistor Control Bit 0 1 Disconnect port 1 pull-up resistor Connect port 1 pull-up resistor
.0
Connect/Disconnect Port 0 Pull-Up Resistor Control Bit 0 1 Disconnect port 0 pull-up resistor Connect port 0 pull-up resistor
4-27
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
SMOD -- Serial I/O Mode Register
Bit Identifier
RESET Value
FE1H, FE0H
5 .5 0 W 8 4 "0" 0 W 8 3 .3 0 R/W 1 2 .2 0 W 8 1 .1 0 W 8 0 .0 0 W 8
7 .7 0 W 8
6 .6 0 W 8
Read/Write Bit Addressing SMOD.7 - .5
Serial I/O Clock Selection and SBUF R/W Status Control Bits 0 0 0 1 1 0 0 1 0 1 0 1 x 0 1 Use an external clock at the SCK pin; Enable SBUF when SIO operation is halted or when SCK goes high Use the TOL0 clock from timer/counter 0; Enable SBUF when SIO operation is halted or when SCK goes high Use the selected CPU clock (fx/4, 8, or 64; 'fx' is the system clock) then, enable SBUF read/write operation. 'x' means 'don't care.' 4.09 kHz clock (fx/210) 262 kHz clock (fx/24); Note: You cannot select a fx/24 clock frequency if you have selected a CPU clock of fx/64
NOTE: All kHz frequency ratings assume a system clock of 4.19 MHz.
SMOD.4
Bit 4 0 Always logic zero
SMOD.3
Initiate Serial I/O Operation Bit 1 Clear IRQS flag and 3-bit clock counter to logic zero; then initiate serial transmission. When SIO transmission starts, this bit is cleared by hardware to logic zero
SMOD.2
Enable/Disable SIO Data Shifter and Clock Counter Bit 0 1 Disable the data shifter and clock counter; retain contents of IRQS flag when serial transmission is completed Enable the data shifter and clock counter; The IRQS flag is set to logic one when serial transmission is completed
SMOD.1
Serial I/O Transmission Mode Selection Bit 0 Receive-only mode 1 Transmit-and-receive mode LSB/MSB Transmission Mode Selection Bit 0 Transmit the most significant bit (MSB) first 1 Transmit the least significant bit (LSB) first
SMOD.0
4-28
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
TMOD0 -- Timer/Counter 0 Mode Register
Bit Identifier
RESET Value
F91H, F90H
0 .4 0 W 8 3 .3 0 W 1 2 .2 0 W 8 1 "0" 0 W 8 0 "0" 0 W 8
3 "0" 0 W 8 Bit 7 0
2 .6 0 W 8
1 .5 0 W 8
Read/Write Bit Addressing .7
Always logic zero
.6 - .4
Timer/Counter 0 Input Clock Selection Bits 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 External clock input at TCL0 pin on rising edge External clock input at TCL0 pin on falling edge Internal system clock (fx) of 4.19 MHz / 210 (4.09 kHz) Selected clock: fx/26 (65.5 kHz) Selected clock: fx/24 (262 kHz) Selected clock: fx (4.19 MHz)
.3
Clear Counter and Resume Counting Control Bit 1 Clear TCNT0, IRQT0, and TOL0 and resume counting immediately. (This bit is cleared automatically when counting starts.)
.2
Enable/Disable Timer/Counter 0 Bit 0 1 Disable timer/counter 0; retain TCNT0 contents Enable timer/counter 0
.1
Bit 1 0 Always logic zero
.0
Bit 0 0 Always logic zero
NOTE: System clock frequency (fx) is assumed to be 4.19 MHz.
4-29
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
TOE0 -- Timer Output Enable Flag
Bit Identifier
RESET Value
F92H
1 0 0 R/W 1/4 0 0 0 W 1/4
3 0 0 R/W 1/4 Bit 3 0
2 TOE0 0 R/W 1/4
Read/Write Bit Addressing .3
Always logic zero
TOE0
Timer/Counter 0 Output Enable Flag 0 1 Disable timer/counter 0 output to the TCLO0 pin Enable timer/counter 0 output to the TCLO0 pin
.1
Bit 1 0 Always logic zero
.0
Bit 0 0 Always logic zero
4-30
KS57C0502/C0504/P0504 MICROCONTROLLER
MEMORY MAP
WDMOD -- Watch-Dog Timer Mode Register
Bit Identifier
RESET Value
F98H, F99H
4 .4 0 W 8 3 .3
0
7 .7 1 W 8
6 .6 0 W 8
5 .5 1 W 8
2 .2 1 W 8
1 .1 0 W 8
0 .0 1 W 8
Read/Write Bit Addressing .7 - .0
W 8
Watch-Dog Timer Enable/Disable Control 5AH Any other value Disable watch-dog timer function Enable watch-dog timer function
WDTCF -- Watch-Dog Timer Flag
Bit Identifier
RESET Value
F9AH
1 "0" 0 0 "0" 0
3 WDTCF 0 W 1
2 "0" 0
Read/Write Bit Addressing .3
Watch-dog timer's counter clear bit 1 Clear and restart the watch-dog timer's counter
NOTE:
Instruction that clear the watch-dog timer ("BITS WDTCF") should be executed at proper points in a program within a given period. If not executed within a given period and watch-dog timer overflows, RESET signal is generated and system is restarted with reset status.
4-31
MEMORY MAP
KS57C0502/C0504/P0504 MICROCONTROLLER
WMOD -- Watch Timer Mode Register
Bit Identifier
RESET Value
F89H, F88H
4 .4 0 W 8 3 "0"
0
7 .7 0 W 8
6 "0" 0 W 8
5 .5 0 W 8
2 .2 0 W 8
1 .1 0 W 8
0 "0" 0 W 8
Read/Write Bit Addressing WMOD.7
R 1
Enable/Disable Buzzer Output Bit 0 1 Disable buzzer (BUZ) signal output Enable buzzer (BUZ) signal output
WMOD.6
Bit 6 0 Always logic zero
WMOD.5 - .4
Output Buzzer Frequency Selection Bits 0 0 1 1 0 1 0 1 2 kHz buzzer (BUZ) signal output 4 kHz buzzer (BUZ) signal output 8 kHz buzzer (BUZ) signal output 16 kHz buzzer (BUZ) signal output
WMOD.3
Bit 3 0 Always logic zero
WMOD.2
Enable/Disable Watch Timer Bit 0 1 Disable watch timer and clear frequency dividing circuits Enable watch timer
WMOD.1
Watch Timer Speed Control Bit 0 1 Normal speed; set IRQW to 0.5 seconds High-speed operation; set IRQW to 3.91 ms
WMOD.0
Bit 0 0 Always logic zero (must be set to zero)
4-32
KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
5
SAM47 INSTRUCTION SET
OVERVIEW The KS57 instruction set includes 1-bit, 4-bit, and 8-bit instructions for data manipulation, logical and arithmetic operations, program control, and CPU control. I/O instructions for peripheral hardware devices are flexible and easy to use. You can substitute symbolic hardware names as the instruction operand in place of the actual address. Other important features of the KS57 instruction set include: -- 1-byte referencing of long instructions (REF instruction) -- Redundant instruction reduction (string effect) -- Skip feature for ADC and SBC instructions Instruction operands conform to the operand format defined for each instruction. Several instructions have multiple operand formats. Predefined values or labels can be used as instruction operands when addressing immediate data. Many of the symbols for specific registers and flags may also be substituted as labels for operations such DA, mema, memb, b, and so on. Using instruction labels can greatly simplify program writing and debugging tasks. INSTRUCTION SET FEATURES In this section, the following KS57 instruction set features are described in detail: -- Instruction reference area -- Instruction redundancy reduction -- Flexible bit manipulation -- ADC and SBC instruction skip condition Instruction Reference Area Using the 1-byte REF (REFerence) instruction, you can reference instructions stored in addresses 0020H-007FH of program memory (the REF instruction look-up table). The location referenced by REF may contain either two 1-byte instructions or a single 2-byte instruction. The starting address of the instruction being referenced must always be an even number. 3-byte instructions such as JP or CALL may also be referenced using REF. To reference these 3-byte instructions, the 2-byte pseudo commands TJP and TCALL must be written to the reference area instead of the normal JP or CALL instruction. The PC is not incremented when a REF instruction is executed. After it executes, the program's instruction execution sequence resumes at the address immediately following the REF instruction. By using REF instructions to execute instructions larger than one byte, as well as branches and subroutines, you can reduce the total number of program steps. To summarize, the REF instruction can be used in three ways: -- Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions; -- Branching to any location by referencing a branch address that is stored in the look-up table; -- Calling subroutines at any location by referencing a call address that is stored in the look-up table.
5-1
INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
Instruction Reference Area (Continued) If necessary, a REF instruction can be circumvented by means of a skip operation prior to the REF in the execution sequence. In addition, the instruction immediately following a REF can also be skipped by using an appropriate reference instruction or instructions. Two-byte instructions that you can reference using a REF instruction are limited to instructions with an execution time of two machine cycles. (An exception to this rule is XCH A,DA. ) In addition, when you use REF to reference two 1-byte instructions stored in the reference area, you must meet specific conditions for the first and second 1-byte instruction. These combinations are described in Table 5-1. Table 5-1. Valid 1-Byte Instruction Combinations for REF Look-Ups First 1-Byte Instruction Instruction LD LD Operand A,@HL @HL,A Second 1-Byte Instruction Instruction INCS DECS INCS DECS INCS INCS DECS INCS DECS INCS INCS DECS INCS DECS Operand L L H H HL X X W W WX L L W W
LD
A,@WX
LD
A,@WL
NOTE:
If the MSB value of the first one-byte instruction is "0", the instruction cannot be referenced by a REF instruction.
5-2
KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
Reducing Instruction Redundancy When redundant instructions such as LD A,#im and LD EA,#imm are used consecutively in a program sequence, only the first instruction is executed. The redundant instructions which follow are ignored, that is, they are handled like a NOP instruction. When LD HL,#imm instructions are used consecutively, redundant instructions are also ignored. In the following example, only the 'LD A, #im' instruction will be executed. The 8-bit load instruction which follows it is interpreted as redundant and is ignored: LD LD A,#im EA,#imm ; ; Load 4-bit immediate data (#im) to accumulator Load 8-bit immediate data (#imm) to extended accumulator
In this example, the statements 'LD A,#2H' and 'LD A,#3H' are ignored: BITR LD LD LD LD EMB A,#1H A,#2H A,#3H 23H,A
; ; ; ;
Execute instruction Ignore, redundant instruction Ignore, redundant instruction Execute instruction, 023H #1H
If consecutive LD HL, #imm instructions (load 8-bit immediate data to the 8-bit memory pointer pair, HL) are detected, only the first LD is executed and the LDs which immediately follow are ignored. For example, LD LD LD LD LD HL,#10H HL,#20H A,#3H EA,#35H @HL,A ; ; ; ; ; HL 10H Ignore, redundant instruction A 3H Ignore, redundant instruction (10H) 3H
If an instruction reference with a REF instruction has a redundancy effect, the following conditions apply: -- If the instruction preceding the REF has a redundancy effect, this effect is cancelled and the referenced instruction is not skipped. -- If the instruction following the REF has a redundancy effect, the instruction following the REF is skipped.
+ PROGRAMMING TIP -- Example of the Instruction Redundancy Effect
ABC ORG LD ORG * * * LD REF * * * REF LD 0020H EA,#30H 0080H ; Stored in REF instruction reference area
EA,#40H ABC
; Redundancy effect is encountered ; No skip (EA #30H)
ABC EA,#50H
; EA #30H ; Skip
5-3
INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
Flexible Bit Manipulation In addition to normal bit manipulation instructions like set and clear, the KS57 instruction set can also perform bit tests, bit transfers, and bit Boolean operations. Bits can also be addressed and manipulated by special bit addressing modes. Three types of bit addressing are supported: -- mema.b -- memb.@L -- @H+DA.b
The parameters of these bit addressing modes are described in more detail in Table 5-2. Table 5-2. Bit Addressing Modes and Parameters Addressing Mode mema.b memb.@L @H+DA.b Addressable Peripherals ERB, EMB, IS1, IS0, IEx, IRQx Ports 0-6 Ports 0-6 and BSC All bit-manipulable peripheral hardware Address Range FB0H-FBFH FF0H-FFFH FC0H-FFFH All bits of the memory bank specified by EMB and SMB that are bit-manipulable
Instructions Which Have Skip Conditions The following instructions have a skip function when an overflow or borrow occurs: XCHI XCHD LDI LDD INCS DECS ADS SBS
If there is an overflow or borrow from the result of an increment or decrement, a skip signal is generated and a skip is executed. However, the carry flag value is unaffected. The instructions BTST, BTSF, and CPSE also generate a skip signal and execute a skip when they meet a skip condition, and the carry flag value is also unaffected. Instructions Which Affect the Carry Flag The only instructions which do not generate a skip signal, but which do affect the carry flag are as follows: ADC SBC SCF RCF CCF
IRET
LDB BAND BOR BXOR RRC
C,(operand) C,(operand) C,(operand) C,(operand)
5-4
KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
ADC and SBC Instruction Skip Conditions The instructions 'ADC A,@HL' and 'SBC A,@HL' can generate a skip signal, and set or clear the carry flag, when they are executed in combination with the instruction 'ADS A,#im'. If an 'ADS A,#im' instruction immediately follows an 'ADC A,@HL' or 'SBC A,@HL' instruction in a program sequence, the ADS instruction does not skip the instruction following ADS, even if it has a skip function. If, however, an 'ADC A,@HL' or 'SBC A,@HL' instruction is immediately followed by an 'ADS A,#im' instruction, the ADC (or SBC) skips on overflow (or if there is no borrow) to the instruction immediately following the ADS, and program execution continues. Table 5-3 contains additional information and examples of the 'ADC A,@HL' and 'SBC A,@HL' skip feature.
Table 5-3. Skip Conditions for ADC and SBC Instructions Sample Instruction Sequences ADC A,@HL ADS A,#im xxx xxx SBC A,@HL ADS A,#im xxx xxx 1 2 3 4 1 2 3 4 If the result of instruction 1 is: Overflow No overflow Borrow No borrow Then, the execution sequence is: 1, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 3, 4 Reason ADS cannot skip instruction 3, even if it has a skip function. ADS cannot skip instruction 3, even if it has a skip function.
5-5
INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
SYMBOLS AND CONVENTIONS Table 5-4. Data Type Symbols Symbol d a b r f i t Data Type Immediate data Address data Bit data Register data Flag data Indirect addressing data memc x 0.5 immediate data Table 5-6. Instruction Operand Notation Symbol DA @ src dst (R) .b im imm # Table 5-5. Register Identifiers Full Register Name 4-bit accumulator 4-bit working registers 8-bit extended accumulator 8-bit memory pointer 8-bit working registers Select register bank 'n' Select memory bank 'n' Carry flag Program status word Port 'n' 'm'-th bit of port 'n' Interrupt priority register Enable memory bank flag Enable register bank flag ID A E, L, H, X, W, Z, Y EA HL WX, YZ, WL SRB n SMB n C PSW Pn Pn.m IPR EMB ERB SB XOR OR AND [(RR)] ADR ADRn R Ra RR RRa RRb RRc mema memb memc Definition Direct address Indirect address prefix Source operand Destination operand Contents of register R Bit location 4-bit immediate data (number) 8-bit immediate data (number) Immediate data prefix 000H-1FFFH immediate address 'n' bit address A, E, L, H, X, W, Z, Y E, L, H, X, W, Z, Y EA, HL, WX, YZ HL, WX, WL HL, WX, YZ WX, WL FB0H-FBFH, FF0H-FFFH FC0H-FFFH Code direct addressing: 0020H-007FH Select bank register (8 bits) Logical exclusive-OR Logical OR Logical AND Contents addressed by RR
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INSTRUCTION SET
OPCODE DEFINITIONS Table 5-7. Opcode Definitions (Direct) Register A E L H X W Z Y EA HL WX YZ r2 0 0 0 0 1 1 1 1 0 0 1 1 r1 0 0 1 1 0 0 1 1 0 1 0 1 r0 0 1 0 1 0 1 0 1 0 0 0 0 Table 5-8. Opcode Definitions (Indirect) Register @HL @WX @WL i2 1 1 1 i1 0 1 1 i0 1 0 1
i = Immediate data for indirect addressing
r = Immediate data for register
CALCULATING ADDITIONAL MACHINE CYCLES FOR SKIPS A machine cycle is defined as one cycle of the selected CPU clock. Three different clock rates can be selected using the PCON register. In this document, the letter 'S' is used in tables when describing the number of additional machine cycles required for an instruction to execute, given that the instruction has a skip function ('S' = skip). The addition number of machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped -- whether it is a 1-byte, 2-byte, or 3-byte instruction. A skip is also done for SMB and SRB instructions. The possible values in additional machine cycles for 'S' for the three cases in which skip conditions occur are as follows: Case 1: No skip Case 2: Skip is 1-byte or 2-byte instruction Case 3: Skip is 3-byte instruction S = 0 cycles S = 1 cycle S = 2 cycles
Please note that REF instructions are skipped in one machine cycle.
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KS57C0502/C0504/P0504 MICROCONTROLLER
HIGH-LEVEL SUMMARY
This section contains a high-level summary of the KS57 instruction set in table format. The tables are designed to familiarize you with the range of instructions that are available in each instruction category. You can also use these tables as a quick-reference source when writing application programs. The following general information is provided for each instruction: -- Instruction name -- Operand(s) -- Brief operation description -- Number of bytes of the instruction and operand(s) -- Number of machine cycles required to execute the instruction
The tables in this section are arranged according to the following instruction categories: -- CPU control instructions -- Program control instructions -- Data transfer instructions -- Logic instructions -- Arithmetic instructions -- Bit manipulation instructions
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Table 5-9. CPU Control Instructions -- High-Level Summary Name SCF RCF CCF EI DI IDLE STOP NOP SMB SRB REF VENTn n n memc EMB (0,1) ERB (0,1) ADR Operand Operation Description Set carry flag to logic one Reset carry flag to logic zero Complement carry flag Enable all interrupts Disable all interrupts Engage CPU idle mode Engage CPU stop mode No operation Select memory bank Select register bank Reference code Load enable memory bank flag (EMB) and the enable register bank flag (ERB) and program counter to vector address, then branch to the corresponding location Bytes 1 1 1 2 2 2 2 1 2 2 1 2 Cycles 1 1 1 2 2 2 2 1 2 2 3 2
Table 5-10. Program Control Instructions -- High-Level Summary Name CPSE Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR JP JPS JR ADR14 ADR12 #im @WX @EA CALL CALLS RET IRET SRET ADR14 ADR11 -- -- -- Operation Description Compare and skip if register equals #im Compare and skip if indirect data memory equals #im Compare and skip if A equals R Compare and skip if A equals indirect data memory Compare and skip if EA equals indirect data memory Compare and skip if EA equals RR Jump to direct address (14 bits) Jump direct in page (12 bits) Jump to immediate address Branch relative to WX register Branch relative to EA Call direct in page (14 bits) Call direct in page (11 bits) Return from subroutine Return from interrupt Return from subroutine and skip Bytes 2 2 2 1 2 2 3 2 1 2 2 3 2 1 1 1 Cycles 2+S 2+S 2+S 1+S 2+S 2+S 3 2 2 3 3 4 3 3 3 3+S
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KS57C0502/C0504/P0504 MICROCONTROLLER
Table 5-11. Data Transfer Instructions -- High-Level Summary Name XCH Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL XCHI XCHD LD A,@HL A,@HL A,#im A,@RRa A,DA A,Ra Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA LDI LDD LDC RRC PUSH POP A,@HL A,@HL EA,@WX EA,@EA A RR SB RR SB Operation Description Exchange A and direct data memory contents Exchange A and register (Ra) contents Exchange A and indirect data memory Exchange EA and direct data memory contents Exchange EA and register pair (RRb) contents Exchange EA and indirect data memory contents Exchange A and indirect data memory contents; increment contents of register L and skip on carry Exchange A and indirect data memory contents; decrement contents of register L and skip on carry Load 4-bit immediate data to A Load indirect data memory contents to A Load direct data memory contents to A Load register contents to A Load 4-bit immediate data to register Load 8-bit immediate data to register Load contents of A to direct data memory Load contents of A to register Load indirect data memory contents to EA Load direct data memory contents to EA Load register contents to EA Load contents of A to indirect data memory Load contents of EA to data memory Load contents of EA to register Load contents of EA to indirect data memory Load indirect data memory to A; increment register L contents and skip on carry Load indirect data memory contents to A; decrement register L contents and skip on carry Load code byte from WX to EA Load code byte from EA to EA Rotate right through carry bit Push register pair onto stack Push SMB and SRB values onto stack Pop to register pair from stack Pop SMB and SRB values from stack Bytes 2 1 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 1 1 1 1 1 1 2 1 2 Cycles 2 1 1 2 2 2 2+S 2+S 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 2+S 2+S 3 3 1 1 2 1 2
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Table 5-12. Logic Instructions -- High-Level Summary Name AND Operand A,#im A,@HL EA,RR RRb,EA OR A, #im A, @HL EA,RR RRb,EA XOR A,#im A,@HL EA,RR RRb,EA COM A Operation Description Logical-AND A immediate data to A Logical-AND A indirect data memory to A Logical-AND register pair (RR) to EA Logical-AND EA to register pair (RRb) Logical-OR immediate data to A Logical-OR indirect data memory contents to A Logical-OR double register to EA Logical-OR EA to double register Exclusive-OR immediate data to A Exclusive-OR indirect data memory to A Exclusive-OR register pair (RR) to EA Exclusive-OR register pair (RRb) to EA Complement accumulator (A) Bytes 2 1 2 2 2 1 2 2 2 1 2 2 2 Cycles 2 1 2 2 2 1 2 2 2 1 2 2 2
Table 5-13. Arithmetic Instructions -- High-Level Summary Name ADC Operand A,@HL EA,RR RRb,EA ADS A, #im EA,#imm A,@HL EA,RR RRb,EA SBC A,@HL EA,RR RRb,EA SBS A,@HL EA,RR RRb,EA DECS INCS R RR R DA @HL RRb Operation Description Add indirect data memory to A with carry Add register pair (RR) to EA with carry Add EA to register pair (RRb) with carry Add 4-bit immediate data to A and skip on carry Add 8-bit immediate data to EA and skip on carry Add indirect data memory to A and skip on carry Add register pair (RR) contents to EA and skip on carry Add EA to register pair (RRb) and skip on carry Subtract indirect data memory from A with carry Subtract register pair (RR) from EA with carry Subtract EA from register pair (RRb) with carry Subtract indirect data memory from A; skip on borrow Subtract register pair (RR) from EA; skip on borrow Subtract EA from register pair (RRb); skip on borrow Decrement register (R); skip on borrow Decrement register pair (RR); skip on borrow Increment register (R); skip on carry Increment direct data memory; skip on carry Increment indirect data memory; skip on carry Increment register pair (RRb); skip on carry Bytes 1 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 1 2 2 1 Cycles 1 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1+S 2+S 1+S 2+S 2+S 1+S
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KS57C0502/C0504/P0504 MICROCONTROLLER
Table 5-14. Bit Manipulation Instructions -- High-Level Summary Name BTST Operand C DA.b mema.b memb.@L @H+DA.b BTSF DA.b mema.b memb.@L @H+DA.b BTSTZ mema.b memb.@L @H+DA.b BITS DA.b mema.b memb.@L @H+DA.b BITR DA.b mema.b memb.@L @H+DA.b BAND C,mema.b C,memb.@L C,@H+DA.b BOR C,mema.b C,memb.@L C,@H+DA.b BXOR C,mema.b C,memb.@L C,@H+DA.b LDB mema.b,C memb.@L,C @H+DA.b,C C,mema.b C,memb.@L C,@H+DA.b Load specified memory bit to carry bit Load specified indirect memory bit to carry bit Load carry bit to a specified memory bit Load carry bit to a specified indirect memory bit Exclusive-OR carry with specified memory bit Logical-OR carry with specified memory bit 2 2 Logical-AND carry flag with specified memory bit Clear specified memory bit to logic zero Set specified memory bit Test specified bit; skip and clear if memory bit is set Test specified memory bit and skip if bit equals "0" 2 2+S Operation Description Test specified bit and skip if carry flag is set Test specified bit and skip if memory bit is set Bytes 1 Cycles 1+S
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INSTRUCTION SET
BINARY CODE SUMMARY This section contains binary code values and operation notation for each instruction in the SAM47 instruction set in an easy-to-read, tabular format. It is intended to be used as a quick-reference source for programmers who are experienced with the SAM47 instruction set. The same binary values and notation are also included in the detailed descriptions of individual instructions later in Section 5. If you are reading this user's manual for the first time, please just scan this very detailed information briefly. Most of the general information you will need to write application programs can be found in the high-level summary tables in the previous section. The following information is provided for each instruction: -- Instruction name -- Operand(s) -- Binary values -- Operation notation The tables in this section are arranged according to the following instruction categories: -- CPU control instructions -- Program control instructions -- Data transfer instructions -- Logic instructions -- Arithmetic instructions -- Bit manipulation instructions
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KS57C0502/C0504/P0504 MICROCONTROLLER
Table 5-15. CPU Control Instructions -- Binary Code Summary Name SCF RCF CCF EI DI IDLE STOP NOP SMB SRB REF VENTn n n memc EMB (0,1) ERB (0,1) ADR Operand
1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 t7 E M B 1 1 1 1 0 1 0 1 0 1 0 0 1 1 1 1 t6 E R B 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 t5
Binary Code
0 0 1 1 1 1 1 1 0 1 1 0 1 0 1 1 t4 0 0 0 1 0 1 0 1 0 1 0 0 1 d3 1 0 t3 1 1 1 1 0 1 0 1 0 1 0 0 1 d2 1 0 t2 1 1 1 1 1 1 1 1 1 1 1 0 0 d1 0 d1 t1 a9 1 0 0 1 0 0 0 1 1 1 1 0 1 d0 1 d0 t0 a8
Operation Notation C1 C0 CC IME 1 IME 0 PCON.2 1 PCON.3 1 No operation SMB n (n = 0, 1, 15) SRB n (n = 0, 1, 2, 3) PC13-0 = memc7-4, memc3-0 <1 ROM (2 x n) 7-6 EMB, ERB ROM (2 x n) 5-4 0, PC13, PC12 ROM (2 x n) 3-0 PC12-8 ROM (2 x n + 1) 7-0 PC7-0 (n = 0, 1, 2, 3, 4, 5, 6, 7)
a13 a12 a11 a10
a7
a6
a5
a4
a3
a2
a1
a0
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
Table 5-16. Program Control Instructions -- Binary Code Summary Name CPSE Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR JP ADR14
1 d3 1 0 1 0 0 1 0 1 1 1 0 a7 1 d2 1 1 1 1 0 1 0 1 1 1 0 a6 0 a6 0 d1 0 1 0 1 1 0 0 0 1 0
Binary Code
1 d0 1 1 1 0 1 1 0 1 0 1 1 0 1 d3 1 1 1 1 1 1 1 1 0 r2 1 d2 1 r2 0 1 0 1 r2 0 0 r1 0 d1 0 r1 0 0 0 0 r1 1 a9 a1 a9 a1 1 r0 1 d0 1 r0 0 0 1 0 0 1 a8 a0 a8 a0
Operation Notation Skip if R = im Skip if (HL) = im Skip if A = R Skip if A = (HL) Skip if A = (HL), E = (HL+1) Skip if EA = RR PC13-0 ADR14
a13 a12 a11 a10 a5 0 a5 a4 1 a4 a3 a2
JPS JR
ADR12 #im * @WX @EA
1 a7
a11 a10 a3 a2
PC13-0 PC13-12 + ADR11-0 PC13-0 ADR (PC-15 to PC+16)
1 0 1 0
1 1 1 1 1 1 a6 1 a6
0 1 0 1 0
1 0 1 0 1
1 0 1 0 1
1 1 1 0 0
0 0 0 0 1 a9 a1 a9 a1
1 0 1 0 1 a8 a0 a8 a0
PC13-0 PC13-8 + (WX) PC13-0 PC13-8 + (EA) [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC13-8 [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC10-8
CALL
ADR14
1 0 a7
a13 a12 a11 a10 a5 1 a5 a4 0 a4 a3 1 a3 a2 a10 a2
CALLS
ADR11
1 a7
First Byte
Condition
a2 a2 a1 a1 a0 a0
* JR #im
0 0
0 0
0 0
1 0
a3 a3
PC PC+2 to PC+16 PC PC-1 to PC-15
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 5-16. Program Control Instructions -- Binary Code Summary (Continued) Name RET Operand -
1 1 0
Binary Code
0 0 1 0 1
Operation Notation PC13-8 (SP + 1) (SP) PC7-0 (SP + 2) (SP + 3) EMB,ERB (SP + 5) (SP + 4) SP SP + 6 PC13-8 (SP + 1) (SP) PC7-0 (SP + 2) (SP + 3) PSW (SP + 4) (SP + 5) SP SP + 6 PC13-8 (SP + 1) (SP) PC7-0 (SP + 3) (SP + 2) EMB,ERB (SP + 5) (SP + 4) SP SP + 6
IRET
-
1
1
0
1
0
1
0
1
SRET
-
1
1
1
0
0
1
0
1
Table 5-17. Data Transfer Instructions -- Binary Code Summary Name XCH Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL XCHI XCHD LD A,@HL A,@HL A,#im A,@RRa A,DA A,Ra
0 a7 0 0 1 a7 1 1 1 0 0 0 1 1 1 a7 1 0 1 a6 1 1 1 a6 1 1 1 0 1 1 0 0 0 a6 1 0 1 a5 1 1 0 a5 0 1 0 0 1 1 1 0 0 a5 0 0
Binary Code
1 a4 0 1 0 a4 1 0 1 0 1 1 1 0 0 a4 1 0 1 a3 1 1 1 a3 1 0 1 0 1 1 d3 1 1 a3 1 1 0 a2 r2 i2 1 a2 1 r2 1 0 0 0 d2 i2 1 a2 1 r2 0 a1 r1 i1 1 a1 0 r1 0 0 1 1 d1 i1 0 a1 0 r1 1 a0 r0 i0 1 a0 0 0 0 1 0 1 d0 i0 0 a0 1 r0
Operation Notation A DA A Ra A (RRa) A DA,E DA + 1 EA RRb A (HL), E (HL + 1) A (HL), then L L+1; skip if L = 0H A (HL), then L L-1; skip if L = 0FH A im A (RRa) A DA A Ra
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
Table 5-17. Data Transfer Instructions -- Binary Code Summary (Continued) Name LD Operand Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA LDI LDD LDC RRC PUSH A,@HL A,@HL EA,@WX EA,@EA A RR SB
1 d3 1 d7 1 a7 1 0 1 0 1 a7 1 1 1 1 a7 1 1 1 0 1 1 1 1 1 0 1 0 1 d2 0 d6 0 a6 1 0 1 0 1 a6 1 1 1 1 a6 1 1 1 0 0 0 1 1 0 0 1 1 0 d1 0 d5 0 a5 0 0 0 0 0 a5 0 1 0 0 a5 0 1 0 0 0 0 0 0 0 1 0 1
Binary Code
1 d0 0 d4 0 a4 1 0 1 0 0 a4 1 1 0 0 a4 1 1 1 0 0 0 0 0 0 0 1 0 1 1 0 d3 1 a3 1 0 1 1 1 a3 1 1 0 1 a3 1 0 1 0 1 1 1 1 1 1 1 0 0 r2 r2 d2 0 a2 1 r2 1 0 1 a2 1 r2 1 1 a2 1 r2 1 0 0 0 1 0 0 r2 1 1 0 r1 r1 d1 0 a1 0 r1 0 0 1 a1 0 r1 0 0 a1 0 r1 0 0 1 1 0 0 0 r1 0 1 1 r0 1 d0 1 a0 1 r0 0 0 0 a0 0 0 0 1 a0 0 0 0 0 0 1 0 0 0 1 1 1
Operation Notation Ra im RR imm DA A Ra A A (HL), E (HL + 1) A DA, E DA + 1 EA RRb (HL) A DA A, DA + 1 E RRb EA (HL) A, (HL + 1) E A (HL), then L L+1; skip if L = 0H A (HL), then L L-1; skip if L = 0FH EA [PC13-8 + (WX)] EA [PC13-8 + (EA)] C A.0, A3 C A.n-1 A.n (n = 1, 2, 3) ((SP-1)) ((SP-2)) (RR), (SP) (SP)-2 ((SP-1)) (SMB), ((SP-2)) (SRB), (SP) (SP)-2
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KS57C0502/C0504/P0504 MICROCONTROLLER
Table 5-17. Data Transfer Instructions -- Binary Code Summary (Concluded) Name POP Operand RR SB
0 1 0 0 1 1 1 0 1
Binary Code
0 1 0 1 1 0 r2 1 1 r1 0 1 0 1 0
Operation Notation RRL (SP), RRH (SP + 1) SP SP + 2 (SRB) (SP), SMB (SP + 1), SP SP + 2
Table 5-18. Logic Instructions -- Binary Code Summary Name AND Operand A,#im A,@HL EA,RR RRb,EA OR A, #im A, @HL EA,RR RRb,EA XOR A,#im A,@HL EA,RR RRb,EA COM A
1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1
Binary Code
1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 d3 1 1 1 1 0 1 d3 1 1 1 1 0 1 d3 1 1 1 1 0 1 1 1 d2 0 1 r2 1 r2 1 d2 0 1 r2 1 r2 1 d2 0 1 r2 1 r2 1 1 0 d1 0 0 r1 0 r1 0 d1 1 0 r1 0 r1 0 d1 1 0 r1 0 r1 0 1 1 d0 1 0 0 0 0 1 d0 0 0 0 0 0 1 d0 1 0 0 0 0 1 1
Operation Notation A A AND im A A AND (HL) EA EA AND RR RRb RRb AND EA A A OR im A A OR (HL) EA EA OR RR RRb RRb OR EA A A XOR im A A XOR (HL) EA EA XOR (RR) RRb RRb XOR EA AA
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INSTRUCTION SET
Table 5-19. Arithmetic Instructions -- Binary Code Summary Name ADC Operand A,@HL EA,RR RRb,EA ADS A, #im EA,#imm A,@HL EA,RR RRb,EA SBC A,@HL EA,RR RRb,EA SBS A,@HL EA,RR RRb,EA DECS R RR INCS R DA @HL RRb
0 1 1 1 1 1 1 d7 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 1 a7 1 0 1 0 1 0 1 0 0 1 d6 0 1 0 1 0 0 1 1 1 1 0 1 0 1 0 1 1 1 1 1 a6 1 1 0 1 0 1 0 1 1 0 d5 1 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 a5 0 1 0
Binary Code
1 1 0 1 0 0 0 d4 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 0 a4 1 0 0 1 1 1 1 0 d3 1 d3 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 a3 1 0 0 1 1 r2 1 r2 d2 0 d2 1 1 r2 1 r2 1 1 r2 1 r2 1 1 r2 1 r2 r2 1 r2 r2 0 a2 1 0 r2 1 0 r1 0 r1 d1 0 d1 1 0 r1 0 r1 0 0 r1 0 r1 0 0 r1 0 r1 r1 0 r1 r1 1 a1 0 1 r1 0 0 0 0 0 d0 1 d0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 r0 0 0 r0 0 a0 1 0 0
Operation Notation C, A A + (HL) + C C, EA EA + RR + C C, RRb RRb + EA + C A A + im; skip on carry EA EA + imm; skip on carry A A + (HL); skip on carry EA EA + RR; skip on carry RRb RRb + EA; skip on carry C,A A - (HL) - C C, EA EA -RR - C C,RRb RRb - EA - C A A - (HL); skip on borrow EA EA - RR; skip on borrow RRb RRb - EA; skip on borrow R R-1; skip on borrow RR RR-1; skip on borrow R R + 1; skip on carry DA DA + 1; skip on carry (HL) (HL) + 1; skip on carry RRb RRb + 1; skip on carry
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 5-20. Bit Manipulation Instructions -- Binary Code Summary Name BTST Operand C DA.b mema.b * memb.@L
1 1 a7 1 1 1 a6 1 0 b1 a5 1
Binary Code
1 b0 a4 1 0 0 a3 1 1 0 a2 0 1 1 a1 0 1 1 a0 1
Operation Notation Skip if C = 1 Skip if DA.b = 1 Skip if mema.b = 1
1 0
1 1 1 0 1 a6 1
1 0 1 b1 b1 a5 1
1 0 1 b0 b0 a4 1
1 a5 1 a3 0 a3 1
0 a4 0 a2 0 a2 0
0 a3 0 a1 1 a1 0
1 a2 1 a0 0 a0 0
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1 Skip if [H + DA.3-0].b = 1 Skip if DA.b = 0 Skip if mema.b = 0
@H+DA.b BTSF DA.b mema.b * memb.@L
1 0 1 a7 1
1 0
1 1 1 0 1
1 0 1 b1 1
1 0 1 b0 1
1 a5 1 a3 1
0 a4 0 a2 1
0 a3 0 a1 0
0 a2 0 a0 1
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 0 Skip if [H + DA.3-0].b = 0 Skip if mema.b = 1 and clear
@H+DA.b BTSTZ mema.b * memb.@L
1 0 1
1 0
1 1 1 0 1 a6 1
1 0 1 b1 b1 a5 1
1 0 1 b0 b0 a4 1
1 a5 1 a3 0 a3 1
1 a4 1 a2 0 a2 1
0 a3 0 a1 0 a1 1
1 a2 1 a0 1 a0 1
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1 and clear Skip if [H + DA.3-0].b =1 and clear DA.b 1 mema.b 1 [memb.7-2 + L.3-2].b [L.1-0] 1 [H + DA.3-0].b 1
@H+DA.b BITS DA.b mema.b * memb.@L @H+DA.b
1 0 1 a7 1
1 0 1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
1 a4 1 a2
1 a3 1 a1
1 a2 1 a0
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INSTRUCTION SET
Table 5-20. Bit Manipulation Instructions -- Binary Code Summary (Continued) Name BITR Operand DA.b mema.b * memb.@L @H+DA.b BAND C,mema.b * C,memb.@L
1 a7 1 1 a6 1 b1 a5 1
Binary Code
b0 a4 1 0 a3 1 0 a2 1 0 a1 1 0 a0 0
Operation Notation DA.b 0 mema.b 0 [memb.7-2 + L3-2].[L.1-0] 0 [H + DA.3-0].b 0 C C AND mema.b C C AND [memb.7-2 + L.3-2]. [L.1-0] C C AND [H + DA.3-0].b C C OR mema.b C C OR [memb.7-2 + L.3-2]. [L.1-0] C C OR [H + DA.3-0].b C C XOR mema.b C C XOR [memb.7-2 + L.3-2]. [L.1-0] C C XOR [H + DA.3-0].b
1 0 1 0 1
1 1 1 0 1
1 0 1 b1 1
1 0 1 b0 1
1 a5 1 a3 0
1 a4 1 a2 1
1 a3 1 a1 0
0 a2 0 a0 1
1 0
1 1 1 0 1
1 0 1 b1 1
1 0 1 b0 1
0 a5 0 a3 0
1 a4 1 a2 1
0 a3 0 a1 1
1 a2 1 a0 0
C,@H+DA.b BOR C,mema.b * C,memb.@L
1 0 1
1 0
1 1 1 0 1
1 0 1 b1 1
1 0 1 b0 1
0 a5 0 a3 0
1 a4 1 a2 1
1 a3 1 a1 1
0 a2 0 a0 1
C,@H+DA.b BXOR C,mema.b * C,memb.@L
1 0 1
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
0 a5 0 a3
1 a4 1 a2
1 a3 1 a1
1 a2 1 a0
C,@H+DA.b
1 0
Second Byte
Bit Addresses
a2 a2 a1 a1 a0 a0
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
FB0H-FBFH FF0H-FFFH
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 5-20. Bit Manipulation Instructions -- Binary Code Summary (Concluded) Name LDB Operand mema.b,C * memb.@L,C @H+DA.b,C C,mema.b * C,memb.@L C,@H+DA.b
1 1 1
Binary Code
1 1 1 0 0
Operation Notation mema.b C memb.7-2 + [L.3-2]. [L.1-0] C H + [DA.3-0].b (C) C mema.b C memb.7-2 + [L.3-2] . [L.1-0] C [H + DA.3-0].b
1 0 1 0 1
1 1 1 b2 1
1 0 1 b1 1
1 0 1 b0 1
1 a5 1 a3 0
1 a4 1 a2 1
0 a3 0 a1 0
0 a2 0 a0 0
1 0 1 0
1 1 1 b2
1 0 1 b1
1 0 1 b0
0 a5 0 a3
1 a4 1 a2
0 a3 0 a1
0 a2 0 a0
Second Byte
Bit Addresses
a2 a2 a1 a1 a0 a0
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
FB0H-FBFH FF0H-FFFH
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
INSTRUCTION DESCRIPTIONS The following section contains detailed information and programming examples for each instruction of the SAM47 instruction set. Information is arranged in a consistent format to improve readability and for use as a quick-reference resource for application programmers. If you are reading this user's manual for the first time, please just scan this very detailed information in order to acquaint yourself with the basic features of the instruction set. The information elements of the instruction description format are as follows: -- -- -- -- -- -- -- Instruction name (mnemonic) Full instruction name Source/destination format of the instruction operand Operation overview (from the "High-Level Summary" table) Textual description of the instruction's effect Binary code overview (from the "Binary Code Summary" table) Programming example(s) to show how the instruction is used
5-23
INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
ADC
ADC Operation:
Add with Carry
dst,src Operand A,@HL EA,RR RRb,EA Operation Summary Add indirect data memory to A with carry Add register pair (RR) to EA with carry Add EA to register pair (RRb) with carry Bytes 1 2 2 Cycles 1 2 2
Description:
The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. If there is an overflow from the most significant bit of the result, the carry flag is set; otherwise, the carry flag is cleared. If 'ADC A,@HL' is followed by an 'ADS A,#im' instruction in a program, ADC skips the ADS instruction if an overflow occurs. If there is no overflow, the ADS instruction is executed normally. (This condition is valid only for 'ADC A,@HL' instructions. If an overflow occurs following an 'ADS A,#im' instruction, the next instruction will not be skipped.) Operand A,@HL EA,RR RRb,EA 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 Binary Code 1 1 0 1 0 1 1 1 1 0 1 1 r2 1 r2 1 0 r1 0 r1 0 0 0 0 0 C, RRb RRb + EA + C Operation Notation C, A A + (HL) + C C, EA EA + RR + C
Examples:
1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is set to "1": SCF ADC JPS EA,HL XXX ; C "1" ; EA 0C3H + 0AAH + 1H = 6EH, C "1" ; Jump to XXX; no skip after ADC
2. If the extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is cleared to "0": RCF ADC JPS EA,HL XXX ; C "0" ; EA 0C3H + 0AAH + 0H = 6EH, C "1" ; Jump to XXX; no skip after ADC
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
ADC Add with Carry
ADC Examples: (Continued) 3. If ADC A,@HL is followed by an ADS A,#im, the ADC skips on carry to the instruction immediately after the ADS. An ADS instruction immediately after the ADC does not skip even if an overflow occurs. This function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the HL register is 9H): RCF LD ADS ADC ADS JPS A,#8H A,#6H A,@HL A,#0AH XXX ; ; ; ; ; C "0" A 8H A 8H + 6H = 0EH A 7H, C "1" Skip this instruction because C = "1" after ADC result
b. 3 + 4 decimal addition (the contents of the address specified by the HL register is 4H): RCF LD ADS ADC ADS A,#3H A,#6H A,@HL A,#0AH ; ; ; ; ; ; ; C "0" A 3H A 3H + 6H = 9H A 9H + 4H + C(0) = 0DH No skip. A 0DH + 0AH = 7H (The skip function for 'ADS A,#im' is inhibited after an 'ADC A,@HL' instruction even if an overflow occurs.)
JPS
XXX
5-25
INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
ADS Add and Skip on Overflow
ADS dst,src Operation: Operand A, #im EA,#imm A,@HL EA,RR RRb,EA Operation Summary Add 4-bit immediate data to A and skip on overflow Add 8-bit immediate data to EA and skip on overflow Add indirect data memory to A and skip on overflow Add register pair (RR) contents to EA and skip on overflow Add EA to register pair (RRb) and skip on overflow Bytes 1 2 1 2 2 Cycles 1+S 2+S 1+S 2+S 2+S
Description:
The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. If there is an overflow from the most significant bit of the result, the skip signal is generated and a skip is executed, but the carry flag value is unaffected. If 'ADS A,#im' follows an 'ADC A,@HL' instruction in a program, ADC skips the ADS instruction if an overflow occurs. If there is no overflow, the ADS instruction is executed normally. This skip condition is valid only for 'ADC A,@HL' instructions, however. If an overflow occurs following an ADS instruction, the next instruction is not skipped. Operand A, #im EA,#imm A,@HL EA,RR RRb,EA 1 1 d7 0 1 1 1 1 0 1 d6 0 1 0 1 0 1 0 d5 1 0 0 0 0 Binary Code 0 0 d4 1 1 1 1 1 d3 1 d3 1 1 1 1 0 d2 0 d2 1 1 r2 1 r2 d1 0 d1 1 0 r1 0 r1 d0 1 d0 1 0 0 0 0 RRb RRb + EA; skip on overflow A A + (HL); skip on overflow EA EA + RR; skip on overflow Operation Notation A A + im; skip on overflow EA EA + imm; skip on overflow
Examples:
1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag = "0": ADS JPS JPS EA,HL XXX YYY ; ; ; ; EA 0C3H + 0AAH = 6DH, C "0" ADS skips on overflow, but carry flag value is not affected. This instruction is skipped because ADS overflowed. Jump to YYY.
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
ADS Add and Skip on Overflow
ADS Examples: (Continued) 2. If the extended accumulator contains the value 0C3H, register pair HL the value 12H, and the carry flag = "0": ADS JPS EA,HL XXX ; EA 0C3H + 12H = 0D5H, C "0" ; Jump to XXX; no skip after ADS.
3. If 'ADC A,@HL' is followed by an 'ADS A,#im', the ADC skips on overflow to the instruction immediately after the ADS. An 'ADS A,#im' instruction immediately after the 'ADC A,@HL' does not skip even if overflow occurs. This function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the HL register is 9H): RCF LD ADS ADC ADS JPS A,#8H A,#6H A,@HL A,#0AH XXX ; ; ; ; ; C "0" A 8H A 8H + 6H = 0EH A 7H, C "1" Skip this instruction because C = "1" after ADC result.
b. 3 + 4 decimal addition (the contents of the address specified by the HL register is 4H): RCF LD ADS ADC ADS A,#3H A,#6H A,@HL A,#0AH ; ; ; ; ; ; ; C "0" A 3H A 3H + 6H = 9H A 9H + 4H + C(0) = 0DH No skip. A 0DH + 0AH = 7H (The skip function for 'ADS A,#im' is inhibited after an 'ADC A,@HL' instruction even if an overflow occurs.)
JPS
XXX
5-27
INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
AND Logical AND
AND Operation: dst,src Operand A,#im A,@HL EA,RR RRb,EA Operation Summary Logical-AND A immediate data to A Logical-AND A indirect data memory to A Logical-AND register pair (RR) to EA Logical-AND EA to register pair (RRb) Bytes 2 1 2 2 Cycles 2 1 2 2
Description:
The source operand is logically ANDed with the destination operand. The result is stored in the destination. The logical AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both "1"; otherwise a "0" bit is stored. The contents of the source are unaffected. Operand A,#im A,@HL EA,RR RRb,EA 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 Binary Code 1 1 1 1 1 1 1 1 d3 1 1 1 1 0 1 d2 0 1 r2 1 r2 0 d1 0 0 r1 0 r1 1 d0 1 0 0 0 0 RRb RRb AND EA A A AND (HL) EA EA AND RR Operation Notation A A AND im
Example:
If the extended accumulator contains the value 0C3H (11000011B) and register pair HL the value 55H (01010101B), the instruction AND EA,HL
leaves the value 41H (01000001B) in the extended accumulator EA .
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
BAND Bit Logical AND
BAND Operation: C,src.b Operand C,mema.b C,memb.@L C,@H+DA.b Operation Summary Logical-AND carry flag with memory bit Bytes 2 2 2 Cycles 2 2 2
Description:
The specified bit of the source is logically ANDed with the carry flag bit value. If the Boolean value of the source bit is a logic zero, the carry flag is cleared to "0"; otherwise, the current carry flag setting is left unaltered. The bit value of the source operand is not affected. Operand C,mema.b * C,memb.@L 1 1 1 Binary Code 1 0 1 0 1 Operation Notation C C AND mema.b C C AND [memb.7-2 + L.3- 2]. [L.1-0] C C AND [H + DA.3-0].b
1
1
1
1
0
1
0
1
0 C,@H+DA.b 1 0
1 1 0
0 1 b1
0 1 b0
a5 0 a3
a4 1 a2
a3 0 a1
a2 1 a0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. The following instructions set the carry flag if P1.0 (port 1.0) is equal to "1" (and assuming the carry flag is already set to "1"): SMB BAND 15 C,P1.0 ; C "1" ; If P1.0 = "1", C "1" ; If P1.0 = "0", C "0"
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
BAND Bit Logical AND
BAND Examples: (Continued) 2. Assume the P1 address is FF1H and the value for register L is 9H (1001B). The address (memb.7-2) is 111100B; (L.3-2) is 10B. The resulting address is 11110010B or FF2H, specifying P2. The bit value for the BAND instruction, (L.1-0) is 01B which specifies bit 1. Therefore, P1.@L = P2.1: LD BAND L,#9H C,P1.@L ; P1.@L is specified as P2.1 ; C AND P2.1
3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3-0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BAND instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG LD BAND EQU 20H.3 H,#2H C,@H+FLAG
; C AND FLAG (20H.3)
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
BITR Bit Reset
BITR Operation: dst.b Operand DA.b mema.b memb.@L @H+DA.b Operation Summary Clear specified memory bit to logic zero Bytes 2 2 2 2 Cycles 2 2 2 2
Description:
A BITR instruction clears to logic zero (resets) the specified bit within the destination operand. No other bits in the destination are affected. Operand DA.b mema.b * memb.@L @H+DA.b 1 a7 1 1 a6 1 b1 a5 1 Binary Code b0 a4 1 0 a3 1 0 a2 1 0 a1 1 0 a0 0 mema.b 0 [memb.7-2 + L3-2].[L.1-0] 0 [H + DA.3-0].b 0 Operation Notation DA.b 0
1 0 1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
1 a4 1 a2
1 a3 1 a1
0 a2 0 a0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. Bit location 30H.2 in the RAM has a current value of logic one. The following instruction clears the third bit in RAM location 30H (bit 2) to logic zero: BITR 30H.2 ; 30H.2 "0"
2. You can use BITR in the same way to manipulate a port address bit: BITR P2.0 ; P2.0 "0"
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
BITR Bit Reset
BITR Examples: (Continued) 3. Assuming that P2.2, P2.3, and P3.0-P3.3 are cleared to "0": BP2 LD BITR INCS JR L,#0AH P0.@L L BP2 ; First, P0.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2
4. If bank 0, location 0A0H.0 is cleared (and regardless of whether the EMB value is logic zero), BITR has the following effect: FLAG EQU
* * *
0A0H.0
BITR
* * *
EMB
LD BITR
H,#0AH @H+FLAG
; Bank 0 (AH + 0H).0 = 0A0H.0 "0" NOTE
Because the BITR instruction is used for output functions, the pin names used in the examples above may vary for different devices in the SAM47 product family.
5-32
KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
BITS Bit Set
BITS Operation: dst.b Operand DA.b mema.b memb.@L @H+DA.b Operation Summary Set specified memory bit Bytes 2 2 2 2 Cycles 2 2 2 2
Description:
This instruction sets the specified bit within the destination without affecting any other bits in the destination. BITS can manipulate any bit that is addressable using direct or indirect addressing modes. Operand DA.b mema.b * memb.@L @H+DA.b 1 a7 1 1 a6 1 b1 a5 1 Binary Code b0 a4 1 0 a3 1 0 a2 1 0 a1 1 1 a0 1 mema.b 1 [memb.7-2 + L.3-2].b [L.1-0] 1 [H + DA.3-0].b 1 Operation Notation DA.b 1
1 0 1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
1 a4 1 a2
1 a3 1 a1
1 a2 1 a0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. Assuming that bit location 30H.2 in the RAM has a current value of "0", the following instruction sets the second bit of location 30H to "1". BITS 30H.2 ; 30H.2 "1"
2. You can use BITS in the same way to manipulate a port address bit: BITS P2.0 ; P2.0 "1"
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
BITS Bit Set
BITS Examples: (Continued) 3. Given that P2.2, P2.3, and P3.0-P3.3 are set to "1": BP2 LD BITS INCS JR L,#0AH P0.@L L BP2 ; First, P0.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2
4. If bank 0, location 0A0H.0, is set to "1" and the EMB = "0", BITS has the following effect: FLAG EQU
* * *
0A0H.0
BITR
* * *
EMB
LD BITS
H,#0AH @H+FLAG
; Bank 0 (AH + 0H).0 = 0A0H.0 "1" NOTE
Because the BITS instruction is used for output functions, pin names used in the examples above may vary for different devices in the SAM47 product family.
5-34
KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
BOR Bit Logical OR
BOR Operation: C,src.b Operand C,mema.b C,memb.@L C,@H+DA.b Operation Summary Logical-OR carry with specified memory bit Bytes 2 2 2 Cycles 2 2 2
Description:
The specified bit of the source is logically ORed with the carry flag bit value. The value of the source is unaffected. Operand C,mema.b * C,memb.@L 1 1 1 Binary Code 1 0 1 1 0 Operation Notation C C OR mema.b C C OR [memb.7-2 + L.3-2]. [L.1-0] C C OR [H + DA.3-0].b
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
0 a5 0 a3
1 a4 1 a2
1 a3 1 a1
0 a2 0 a0
C,@H+DA.b
1 0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. The carry flag is logically ORed with the P1.0 value: RCF BOR C,P1.0 ; C "0" ; If P1.0 = "1", then C "1"; if P1.0 = "0", then C "0"
2. The P1 address is FF1H and register L contains the value 9H (1001B). The address (memb.7-2) is 111100B and (L.3-2) = 10B. The resulting address is 11110010B or FF2H, specifying P2. The bit value for the BOR instruction, (L.1-0) is 01B which specifies bit 1. Therefore, P1.@L = P2.1: LD BOR L,#9H C,P1.@L ; P1.@L is specified as P2.1; C OR P2.1
5-35
INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
BOR Bit Logical OR
BOR Examples: (Continued) 3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3-0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BOR instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG EQU LD BOR 20H.3 H,#2H C,@H+FLAG
;
C OR FLAG (20H.3)
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
BTSF Bit Test
BTSF Operation: dst.b Operand DA.b mema.b memb.@L @H+DA.b
Skip on False
Operation Summary Test specified memory bit and skip if bit equals "0"
Bytes 2 2 2 2
Cycles 2+S 2+S 2+S 2+S
Description:
The specified bit within the destination operand is tested. If it is a "0", the BTSF instruction skips the instruction which immediately follows it; otherwise the instruction following the BTSF is executed. The destination bit value is not affected. Operand DA.b mema.b * memb.@L 1 a7 1 1 a6 1 b1 a5 1 Binary Code b0 a4 1 0 a3 1 0 a2 0 1 a1 0 0 a0 0 Skip if mema.b = 0 Operation Notation Skip if DA.b = 0
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
0 a4 0 a2
0 a3 0 a1
0 a2 0 a0
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 0 Skip if [H + DA.3-0].b = 0
@H + DA.b
1 0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. If RAM bit location 30H.2 is set to logic zero, the following instruction sequence will cause the program to continue execution from the instruction identifed as LABEL2: BTSF RET JP 30H.2 LABEL2 ; If 30H.2 = "0", then skip ; If 30H.2 = "1", return
2. You can use BTSF in the same way to manipulate a port pin address bit: BTSF RET JP P2.0 LABEL3 ; If P2.0 = "0", then skip ; If P2.0 = "1", then return
5-37
INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
BTSF Bit Test and Skip on False
BTSF Examples: (Continued) 3. P2.2, P2.3 and P3.0-P3.3 are tested: BP2 LD BTSF RET INCS JR L,#0AH P0.@L ; First, P0.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2
L BP2
4. Bank 0, location 0A0H.0, is tested and (regardless of the current EMB value) BTSF has the following effect: FLAG EQU
* * *
0A0H.0
BITR
* * *
EMB
LD BTSF RET
* * *
H,#0AH @H+FLAG
; If bank 0 (AH + 0H).0 = 0A0H.0 = "0", then skip
5-38
KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
BTST Bit Test and Skip on True
BTST Operation: dst.b Operand C DA.b mema.b memb.@L @H+DA.b Operation Summary Test carry bit and skip if set (= "1") Test specified bit and skip if memory bit is set Bytes 1 2 2 2 2 Cycles 1+S 2+S 2+S 2+S 2+S
Description:
The specified bit within the destination operand is tested. If it is "1", the instruction that immediately follows the BTST instruction is skipped; otherwise the instruction following the BTST instruction is executed. The destination bit value is not affected. Operand C DA.b mema.b * memb.@L 1 1 a7 1 1 1 a6 1 0 b1 a5 1 Binary Code 1 b0 a4 1 0 0 a3 1 1 0 a2 0 1 1 a1 0 1 1 a0 1 Skip if mema.b = 1 Operation Notation Skip if C = 1 Skip if DA.b = 1
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
0 a4 0 a2
0 a3 0 a1
1 a2 1 a0
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1 Skip if [H + DA.3-0].b = 1
@H+DA.b
1 0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. If RAM bit location 30H.2 is set to logic zero, the following instruction sequence will execute the RET instruction: BTST RET JP 30H.2 LABEL2 ; If 30H.2 = "1", then skip ; If 30H.2 = "0", return
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
BTST Bit Test and Skip on True
BTST Examples: (Continued) 2. You can use BTST in the same way to manipulate a port pin address bit: BTST RET JP P2.0 LABEL3 ; If P2.0 = "1", then skip ; If P2.0 = "0", then return
3. Assume that P2.2, P2.3 and P3.0-P3.3 are cleared to "0": BP2 LD BTST RET INCS JR L,#0AH P0.@L ; First, P0.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2
L BP2
4. Bank 0, location 0A0H.0, is tested and (regardless of the current EMB value) BTST has the following effect: FLAG EQU
* * *
0A0H.0
BITR
* * *
EMB
LD BTST RET
* * *
H,#0AH @H+FLAG
; If bank 0 (AH + 0H).0 = 0A0H.0 = "1", then skip
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
BTSTZ Bit Test and Skip on True; Clear Bit
BTSTZ Operation: dst.b Operand mema.b memb.@L @H+DA.b Operation Summary Test specified bit; skip and clear if memory bit is set Bytes 2 2 2 Cycles 2+S 2+S 2+S
Description:
The specified bit within the destination operand is tested. If it is a "1", the instruction immediately following the BTSTZ instruction is skipped; otherwise the instruction following the BTSTZ is executed. The destination bit value is cleared. Operand mema.b * memb.@L 1 1 1 Binary Code 1 1 1 0 1 Operation Notation Skip if mema.b = 1 and clear
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
1 a4 1 a2
0 a3 0 a1
1 a2 1 a0
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1 and clear Skip if [H + DA.3-0].b =1 and clear
@H+DA.b
1 0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. Port pin P2.0 is toggled by checking the P2.0 value (level): BTSTZ BITS JP P2.0 P2.0 LABEL3 ; If P2.0 = "1", then P2.0 "0" and skip ; If P2.0 = "0", then P2.0 "1"
2. Assume that port pins P2.2, P2.3 and P3.0-P3.3 are toggled: BP2 LD BTSTZ RET INCS JR L,#0AH P0.@L ; First, P0.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2
L BP2
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
BTSTZ Bit Test and Skip on True; Clear Bit
BTSTZ Examples: (Continued) 3. Bank 0, location 0A0H.0, is tested and EMB = "0": FLAG EQU
* * *
0A0H.0
BITR
* * *
EMB
LD BTSTZ BITS
H,#0AH @H+FLAG @H+FLAG
; ;
If bank 0 (AH + 0H).0 = 0A0H.0 = "1", clear and skip If 0A0H.0 = "0", then 0A0H.0 "1"
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
BXOR Bit Exclusive OR
BXOR Operation: C,src.b Operand C,mema.b C,memb.@L C,@H+DA.b Operation Summary Exclusive-OR carry with memory bit Bytes 2 2 2 Cycles 2 2 2
Description:
The specified bit of the source is logically XORed with the carry bit value. The resultant bit is written to the carry flag. The source value is unaffected. Operand C,mema.b * C,memb.@L 1 1 1 Binary Code 1 0 1 1 1 Operation Notation C C XOR mema.b C C XOR [memb.7-2 + L.3-2]. [L.1-0] C C XOR [H + DA.3-0].b
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
0 a5 0 a3
1 a4 1 a2
1 a3 1 a1
1 a2 1 a0
C,@H+DA.b
1 0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
Examples:
1. The carry flag is logically XORed with the P1.0 value: RCF BXOR C,P1.0 ; C "0" ; If P1.0 = "1", then C "1"; if P1.0 = "0", then C "0"
2. The P1 address is FF1H and register L contains the value 9H (1001B). The address (memb.7-2) is 111100B and (L.3-2) = 10B. The resulting address is 11110010B or FF2H, specifying P2. The bit value for the BXOR instruction, (L.1-0) is 01B which specifies bit 1. Therefore, P1.@L = P2.1: LD BXOR L,#9H C,P1.@L ; P1.@L is specified as P2.1; C XOR P2.1
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
BXOR Bit Exclusive OR
BXOR Examples: (Continued) 3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3-0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BOR instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG EQU 20H.3 LD H,#2H BXOR C,@H+FLAG
;
C XOR FLAG (20H.3)
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
CALL Call Procedure
CALL Operation: dst Operand ADR14 Operation Summary Call direct in page (14 bits) Bytes 3 Cycles 4
Description:
CALL calls a subroutine located at the destination address. The instruction adds three to the program counter to generate the return address and then pushes the result onto the stack, decrementing the stack pointer by six. The EMB and ERB are also pushed to the stack. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 16-Kbyte program memory address space. Operand ADR14 1 0 a7 1 1 a6 0 a5 Binary Code 1 a4 1 a3 0 a2 1 a9 a1 1 a8 a0 a13 a12 a11 a10 Operation Notation [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC13-8
Example:
The stack pointer value is 00H and the label 'PLAY' is assigned to program memory location 0E3FH. Executing the instruction CALL PLAY
at location 0123H generates the following values: SP 0FFH 0FEH 0FDH 0FCH 0FBH 0FAH PC = = = = = = = = 0FAH 0H EMB, ERB 2H 6H 0H 1H 0E3FH
Data is written to stack locations 0FFH-0FAH as follows: 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH PC11 - PC8 0 PC13 - PC12 PC3 - PC0 PC7 - PC4 0 EMB ERB 0 0 0
0
0 0
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
CALLS Call Procedure (Short)
CALLS Operation: dst Operand ADR11 Operation Summary Call direct in page (11 bits) Bytes 2 Cycles 3
Description:
The CALLS instruction unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction. Then, it pushes the result onto the stack, decrementing the stack pointer six times. The higher bits of the PC, with the exception of the lower 11 bits, are cleared. The subroutine call must therefore be located within the 2-Kbyte block (0000H-07FFH) of program memory. Operand ADR11 1 a7 1 a6 1 a5 Binary Code 0 a4 1 a3 a10 a2 a9 a1 a8 a0 Operation Notation [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC10-8
Example:
The stack pointer value is 00H and the label 'PLAY' is assigned to program memory location 0345H. Executing the instruction CALLS PLAY
at location 0123H will generate the following values: SP 0FFH 0FEH 0FDH 0FCH 0FBH 0FAH PC = = = = = = = = 0FAH 0H EMB, ERB 2H 5H 0H 1H 0345H
Data is written to stack locations 0FFH-0FAH as follows: 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH 0 0 PC10 - PC8 0 0 0 PC3 - PC0 PC7 - PC4 0 EMB ERB 0 0 0
0 0
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
CCF Complement Carry Flag
CCF Operation: Operand -- Operation Summary Complement carry flag Bytes 1 Cycles 1
Description:
The carry flag is complemented; if C = "1" it is changed to C = "0" and vice-versa. Operand -- 1 1 0 Binary Code 1 0 1 1 0 Operation Notation CC
Example:
If the carry flag is logic zero, the instruction CCF changes the value to logic one.
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
COM Complement Accumulator
COM Operation: A Operand A Operation Summary Complement accumulator (A) Bytes 2 Cycles 2
Description:
The accumulator value is complemented; if the bit value of A is "1", it is changed to "0" and vice versa. Operand A 1 0 1 0 0 1 Binary Code 1 1 1 1 1 1 0 1 1 1 Operation Notation AA
Example:
If the accumulator contains the value 4H (0100B), the instruction COM A
leaves the value 0BH (1011B) in the accumulator.
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
CPSE Compare and Skip if Equal
CPSE Operation: dst,src Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR Operation Summary Compare and skip if register equals #im Compare and skip if indirect data memory equals #im Compare and skip if A equals R Compare and skip if A equals indirect data memory Compare and skip if EA equals indirect data memory Compare and skip if EA equals RR Bytes 2 2 2 1 2 2 Cycles 2+S 2+S 2+S 1+S 2+S 2+S
Description:
CPSE compares the source operand (subtracts it from) the destination operand, and skips the next instruction if the values are equal. Neither operand is affected by the comparison. Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR 1 d3 1 0 1 0 0 1 0 1 1 1 d2 1 1 1 1 0 1 0 1 1 0 d1 0 1 0 1 1 0 0 0 1 Binary Code 1 d0 1 1 1 0 1 1 0 1 0 1 0 1 d3 1 1 1 1 1 1 1 0 r2 1 d2 1 r2 0 1 0 1 r2 0 r1 0 d1 0 r1 0 0 0 0 r1 1 r0 1 d0 1 r0 0 0 1 0 0 Skip if EA = RR Skip if A = (HL) Skip if A = (HL), E = (HL+1) Skip if A = R Skip if (HL) = im Operation Notation Skip if R = im
Example:
The extended accumulator contains the value 34H and register pair HL contains 56H. The second instruction (RET) in the instruction sequence CPSE RET EA,HL
is not skipped. That is, the subroutine returns because the result of the comparison is 'not equal.'
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
DECS Decrement and Skip on Borrow
DECS Operation: dst Operand R RR Operation Summary Decrement register (R); skip on borrow Decrement register pair (RR); skip on borrow Bytes 1 2 Cycles 1+S 2+S
Description:
The destination is decremented by one. An original value of 00H will underflow to 0FFH. If a borrow occurs, a skip is executed. The carry flag value is unaffected. Operand R RR 0 1 1 1 1 1 0 0 0 Binary Code 0 1 1 1 1 1 r2 1 r2 r1 0 r1 r0 0 0 Operation Notation R R-1; skip on borrow RR RR-1; skip on borrow
Examples:
1. Register pair HL contains the value 7FH (01111111B). The following instruction leaves the value 7EH in register pair HL: DECS HL
2. Register A contains the value 0H. The following instruction sequence leaves the value 0FFH in register A. Because a "borrow" occurs, the 'CALL PLAY1' instruction is skipped and the 'CALL PLAY2' instruction is executed: DECS CALL CALL A PLAY1 PLAY2 ; "Borrow" occurs ; Skipped ; Executed
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
DI Disable Interrupts
DI Operation: Operand -- Operation Summary Disable all interrupts Bytes 2 Cycles 2
Description:
Bit 3 of the interrupt priority register IPR, IME, is cleared to logic zero, disabling all interrupts. Interrupts can still set their respective interrupt status latches, but the CPU will not directly service them. Operand -- 1 1 1 0 1 1 Binary Code 1 1 1 0 1 0 1 1 0 0 Operation Notation IME 0
Example:
If the IME bit (bit 3 of the IPR) is logic one (e.g., all instructions are enabled), the instruction DI sets the IME bit to logic zero, disabling all interrupts.
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
EI Enable Interrupts
EI Operation: Operand -- Operation Summary Enable all interrupts Bytes 2 Cycles 2
Description:
Bit 3 of the interrupt priority register IPR (IME) is set to logic one. This allows all interrupts to be serviced when they occur, assuming they are enabled. If an interrupt's status latch was previously enabled by an interrupt, this interrupt can also be serviced. Operand -- 1 1 1 0 1 1 Binary Code 1 1 1 0 1 0 1 1 1 0 Operation Notation IME 1
Example:
If the IME bit (bit 3 of the IPR) is logic zero (e.g., all instructions are disabled), the instruction EI sets the IME bit to logic one, enabling all interrupts.
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
IDLE Idle Operation
IDLE Operation: Operand -- Operation Summary Engage CPU idle mode Bytes 2 Cycles 2
Description:
IDLE causes the CPU clock to stop while the system clock continues oscillating by setting bit 2 of the power control register (PCON). After an IDLE instruction has been executed, peripheral hardware remains operative. In application programs, an IDLE instruction should be immediately followed by at least three NOP instructions. This ensures an adequate time interval for the clock to stabilize before the next instruction is executed. Operand -- 1 1 1 0 1 1 Binary Code 1 0 1 0 1 0 1 1 1 1 Operation Notation PCON.2 1
Example:
The instruction sequence IDLE NOP NOP NOP sets bit 2 of the PCON register to logic one, stopping the CPU clock. The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed.
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
INCS Increment and Skip on Carry
INCS Operation: dst Operand R DA @HL RRb Operation Summary Increment register (R); skip on carry Increment direct data memory; skip on carry Increment indirect data memory; skip on carry Increment register pair (RRb); skip on carry Bytes 1 2 2 1 Cycles 1+S 2+S 2+S 1+S
Description:
The instruction INCS increments the value of the destination operand by one. An original value of 0FH will, for example, overflow to 00H. If a carry occurs, the next instruction is skipped. The carry flag value is unaffected. Operand R DA @HL RRb 0 1 a7 1 0 1 1 1 a6 1 1 0 0 0 a5 0 1 0 Binary Code 1 0 a4 1 0 0 1 1 a3 1 0 0 r2 0 a2 1 0 r2 r1 1 a1 0 1 r1 r0 0 a0 1 0 0 RRb RRb + 1; skip on carry (HL) (HL) + 1; skip on carry Operation Notation R R + 1; skip on carry DA DA + 1; skip on carry
Example:
Register pair HL contains the value 7EH (01111110B). RAM location 7EH contains 0FH. The instruction sequence INCS INCS INCS @HL HL @HL ; 7EH "0" ; Skip ; 7EH "1"
leaves the register pair HL with the value 7EH and RAM location 7EH with the value 1H. Because a carry occurred, the second instruction is skipped. The carry flag value remains unchanged.
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
IRET Return from Interrupt
IRET Operation: Operand -- Operation Summary Return from interrupt Bytes 1 Cycles 3
Description:
IRET is used at the end of an interrupt service routine. It pops the PC values successively from the stack and restores them to the program counter. The stack pointer is incremented by six and the PSW, enable memory bank (EMB) bit, and enable register bank (ERB) bit are also automatically restored to their pre-interrupt values. Program execution continues from the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower-level or same-level interrupt was pending when the IRET was executed, IRET will be executed before the pending interrupt is processed. Because the 'a14' bit of an interrupt return address is not stored in the stack, this bit location is always interpreted as a logic zero. The start address in the ROM must for this reason be 3FFFH. Operand -- 1 1 0 Binary Code 1 0 1 0 1 Operation Notation PC13-8 (SP + 1) (SP) PC7-0 (SP + 2) (SP + 3) PSW (SP + 4) (SP + 5) SP SP + 6
Example:
The stack pointer contains the value 0FAH. An interrupt is detected in the instruction at location 0122H. RAM locations 0FDH, 0FCH, and 0FAH contain the values 2H, 3H, and 1H, respectively. The instruction IRET leaves the stack pointer with the value 00H and the program returns to continue execution at location 123H. During a return from interrupt, data is popped from the stack to the program counter. The data in stack locations 0FFH-0FAH is organized as follows: 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH IS1 C 0 PC11 - PC8 0 PC13 - PC12 PC3 - PC0 PC7 - PC4 IS0 SC2 EMB SC1 ERB SC0
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
JP Jump
JP Operation: dst Operand ADR14 Operation Summary Jump to direct address (14 bits) Bytes 3 Cycles 3
Description:
JP causes an unconditional branch to the indicated address by replacing the contents of the program counter with the address specified in the destination operand. The destination can be anywhere in the 16-Kbyte program memory address space. Operand ADR14 1 0 a7 1 0 a6 0 a5 Binary Code 1 a4 1 a3 0 a2 1 a9 a1 1 a8 a0 a13 a12 a11 a10 Operation Notation PC13-0 ADR14
Example:
The label 'SYSCON' is assigned to the instruction at program location 07FFH. The instruction JP SYSCON
at location 0123H loads the program counter with the value 07FFH.
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
JPS Jump (Short)
JPS Operation: dst Operand ADR12 Operation Summary Jump direct in page (12 bits) Bytes 2 Cycles 2
Description:
JPS causes an unconditional branch to the indicated address within the 4-Kbyte program memory address space. Bits 0-11 of the program counter are replaced with the directly specified address. The destination address for this jump is specified to the assembler by a label or by an actual address in program memory. Operand ADR12 1 a7 0 a6 0 a5 Binary Code 1 a4 a11 a10 a3 a2 a9 a1 a8 a0 Operation Notation PC13-0 PC13-12 + ADR11- 0
Example:
The label 'SUB' is assigned to the instruction at program memory location 00FFH. The instruction JPS SUB
at location 0EABH will load the program counter with the value 00FFH. Normally, the JPS instruction jumps to the address in the block in which the instruction is located. If the first byte of the instruction code is located at address xFFEH or xFFFH, the instruction will jump to the next block. If the instruction 'JPS SUB' were located instead at program memory address 0FFEH or 0FFFH, the instruction 'JPS SUB' would load the PC with the value 10FFH, causing a program malfunction.
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
JR Jump Relative (Very Short)
JR Operation: dst Operand #im @WX @EA Operation Summary Branch to relative immediate address Branch relative to contents of WX register Branch relative to contents of EA Bytes 1 2 2 Cycles 2 3 3
Description:
JR causes the relative address to be added to the program counter and passes control to the instruction whose address is now in the PC. The range of the relative address is current PC - 15 to current PC + 16. The destination address for this jump is specified to the assembler by a label, an actual address, or by immediate data using a plus sign (+) or a minus sign (-). For immediate addressing, the (+) range is from 2 to 16 and the (-) range is from -1 to -15. If a 0, 1, or any other number that is outside these ranges are used, the assembler interprets it as an error. For JR @WX and JR @EA branch relative instructions, the valid range for the relative address is 0H-0FFH. The destination address for these jumps can be specified to the assembler by a label that lies anywhere within the current 256-byte block. Normally, the 'JR @WX' and 'JR @EA' instructions jump to the address in the page in which the instruction is located. However, if the first byte of the instruction code is located at address xxFEH or xxFFH, the instruction will jump to the next page. Operand #im * @WX @EA 1 0 1 0 1 1 1 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1 0 PC13-0 PC13-8 + (EA) Binary Code Operation Notation PC13-0 ADR (PC-15 to PC+16) PC13-0 PC13-8 + (WX)
First Byte
Condition a2 a2 a1 a1 a0 a0 PC PC+2 to PC+16 PC PC-1 to PC-15
* JR #im
0 0
0 0
0 0
1 0
a3 a3
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
JR Jump Relative (Very Short)
JR Examples: (Continued) 1. A short form for a relative jump to label 'KK' is the instruction JR KK where 'KK' must be within the allowed range of current PC-15 to current PC+16. The JR instruction has in this case the effect of an unconditional JP instruction. 2. In the following instruction sequence, if the instruction 'LD WX, #02H' were to be executed in place of 'LD WX,#00H', the program would jump to 1002H and 'JPS BBB' would be executed. If 'LD EA,#04H' were to be executed, the jump would be to1004H and 'JPS CCC' would be executed. ORG JPS JPS JPS JPS LD LD ADS JR 1000H AAA BBB CCC DDD WX,#00H EA,WX WX,EA @WX
; WX 00H ; WX (WX) + (WX) ; Current PC13-8 (10H) + WX (00H) = 1000H ; Jump to address 1000H and execute JPS AAA
3. Here is another example: ORG LD LD LD LD LD JPS LD JR 1100H A,#0H A,#1H A,#2H A,#3H 30H,A YYY EA,#00H @EA
; Address 30H A ; EA 00H ; Jump to address 1100H ; Address 30H 00H
XXX
If 'LD EA,#01H' were to be executed in place of 'LD EA,#00H', the program would jump to 1001H and address 30H would contain the value 1H. If 'LD EA,#02H' were to be executed, the jump would be to 1002H and address 30H would contain the value 2H.
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
LD Load
LD Operation: dst,src Operand A,#im A,@RRa A,DA A,Ra Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA Operation Summary Load 4-bit immediate data to A Load indirect data memory contents to A Load direct data memory contents to A Load register contents to A Load 4-bit immediate data to register Load 8-bit immediate data to register Load contents of A to direct data memory Load contents of A to register Load indirect data memory contents to EA Load direct data memory contents to EA Load register contents to EA Load contents of A to indirect data memory Load contents of EA to data memory Load contents of EA to register Load contents of EA to indirect data memory Bytes 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 Cycles 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2
Description:
The contents of the source are loaded into the destination. The source's contents are unaffected.If an instruction such as 'LD A,#im' (LD EA,#imm) or 'LD HL,#imm' is written more than two times in succession, only the first LD will be executed; the other similar instructions that immediately follow the first LD will be treated like a NOP. This is called the 'redundancy effect' (see examples below). Operand A,#im A,@RRa A,DA A,Ra Ra,#im 1 1 1 a7 1 0 1 d3 0 0 0 a6 1 0 1 d2 1 0 0 a5 0 0 0 d1 Binary Code 1 0 0 a4 1 0 1 d0 d3 1 1 a3 1 1 1 1 d2 i2 1 a2 1 r2 0 r2 d1 i1 0 a1 0 r1 0 r1 d0 i0 0 a0 1 r0 1 r0 Ra im A Ra Operation Notation A im A (RRa) A DA
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
LD Load
LD Description: Operand RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA 1 d7 1 a7 1 0 1 0 1 a7 1 1 1 1 a7
1 1
(Continued)
Binary Code 0 d6 0 a6 1 0 1 0 1 a6 1 1 1 1 a6
1 1
Operation Notation r2 d2 0 a2 1 r2 1 0 1 a2 1 r2 1 1 a2
1 r2
0 d5 0 a5 0 0 0 0 0 a5 0 1 0 0 a5
0 1
0 d4 0 a4 1 0 1 0 0 a4 1 1 0 0 a4
1 1
0 d3 1 a3 1 0 1 1 1 a3 1 1 0 1 a3
1 0
r1 d1 0 a1 0 r1 0 0 1 a1 0 r1 0 0 a1
0 r1
1 d0 1 a0 1 r0 0 0 0 a0 0 0 0 1 a0
0 0
RR imm DA A Ra A A (HL), E (HL + 1) A DA, E DA + 1 EA RRb (HL) A DA A, DA + 1 E RRb EA (HL) A, (HL + 1) E
1 0
1 0
0 0
1 0
1 0
1 0
0 0
0 0
Examples:
1. RAM location 30H contains the value 4H. The RAM location values are 40H, 41H and 0AH, 3H respectively. The following instruction sequence leaves the value 40H in point pair HL, 0AH in the accumulator and in RAM location 40H, and 3H in register E. LD LD LD LD LD HL,#30H A,@HL HL,#40H EA,@HL @HL,A ; ; ; ; ; HL 30H A 4H HL 40H A 0AH, E 3H RAM (40H) 0AH
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
LD Load
LD Examples: (Continued) 2. If an instruction such as LD A,#im (LD EA,#imm) or LD HL,#imm is written more than two times in succession, only the first LD is executed; the next instructions are treated as NOPs. Here are two examples of this 'redundancy effect': LD LD LD LD LD LD LD LD LD A,#1H EA,#2H A,#3H 23H,A HL,#10H HL,#20H A,#3H EA,#35 @HL,A ; ; ; ; ; ; ; ; ; A 1H NOP NOP (23H) 1H HL 10H NOP A 3H NOP (10H) 3H
The following table contains descriptions of special characteristics of the LD instruction when used in different addressing modes: Instruction LD A,#im Operation Description and Guidelines Because the 'redundancy effect' occurs with instructions like LD EA,#imm, if this instruction is used consecutively, the second and additional instructions of the same type will be treated like NOPs.
LD A,@RRa Load the data memory contents pointed to by 8-bit RRa register pairs (HL, WX, WL) to the A register. LD A,DA LD A,Ra LD Ra,#im LD RR,#imm Load direct data memory contents to the A register. Load 4-bit register Ra (E, L, H, X, W, Z, Y) to the A register. Load 4-bit immediate data into the Ra register (E, L, H, X, W, Y, Z). Load 8-bit immediate data into the Ra register (EA, HL, WX, YZ). There is a redundancy effect if the operation addresses the HL or EA registers. Load contents of register A to direct data memory address. Load contents of register A to 4-bit Ra register (E, L, H, X, W, Z, Y).
LD DA,A LD Ra,A
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
LD Load
LD Examples: Instruction LD EA,@HL Operation Description and Guidelines Load data memory contents pointed to by 8-bit register HL to the A register, and the contents of HL+1 to the E register. The contents of register L must be an even number. If the number is odd, the LSB of register L is recognized as a logic zero (an even number), and it is not replaced with the true value. For example, 'LD HL,#36H' loads immediate 36H to HL and the next instruction 'LD EA,@HL' loads the contents of 36H to register A and the contents of 37H to register E. Load direct data memory contents of DA to the A register, and the next direct data memory contents of DA + 1 to the E register. The DA value must be an even number. If it is an odd number, the LSB of DA is recognized as a logic zero (an even number), and it is not replaced with the true value. For example, 'LD EA,37H' loads the contents of 36H to the A register and the contents of 37H to the E register. Load 8-bit RRb register (HL, WX, YZ) to the EA register. H, W, and Y register values are loaded into the E register, and the L, X, and Z values into the A register. Load A register contents to data memory location pointed to by the 8-bit HL register value. Load the A register contents to direct data memory and the E register contents to the next direct data memory location. The DA value must be an even number. If it is an odd number, the LSB of the DA value is recognized as logic zero (an even number), and is not replaced with the true value. Load contents of EA to the 8-bit RRb register (HL, WX, YZ). The E register is loaded into the H, W, and Y register and the A register into the L, X, and Z register. Load the A register to data memory location pointed to by the 8-bit HL register, and the E register contents to the next location, HL + 1. The contents of the L register must be an even number. If the number is odd, the LSB of the L register is recognized as logic zero (an even number), and is not replaced with the true value. For example, 'LD HL,#36H' loads immediate 36H to register HL; the instruction 'LD @HL,EA' loads the contents of A into address 36H and the contents of E into address 37H. (Concluded)
LD EA,DA
LD EA,RRb
LD @HL,A
LD DA,EA
LD RRb,EA
LD @HL,EA
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
LDB Load Bit
LDB LDB Operation: dst,src.b dst.b,src Operand mema.b,C memb.@L,C @H+DA.b,C C,mema.b C,memb.@L C,@H+DA.b Load memory bit to a specified carry bit Load indirect memory bit to a specified carry bit Operation Summary Load carry bit to a specified memory bit Load carry bit to a specified indirect memory bit Bytes 2 2 2 2 2 2 Cycles 2 2 2 2 2 2
Description:
The Boolean variable indicated by the first or second operand is copied into the location specified by the second or first operand. One of the operands must be the carry flag; the other can be any directly or indirectly addressable bit. The source is unaffected. Operand mema.b,C * memb.@L,C @H+DA.b,C C,mema.b* C,memb.@L C,@H+DA.b 1 1 1 Binary Code 1 1 1 0 0 Operation Notation mema.b C memb.7-2 + [L.3-2]. [L.1-0] C H + [DA.3-0].b (C) C mema.b C memb.7-2 + [L.3-2] . [L.1-0] C [H + DA.3-0].b
1 0 1 0 1 1 0 1 0
1 1 1 b2 1 1 1 1 b2
1 0 1 b1 1 1 0 1 b1
1 0 1 b0 1 1 0 1 b0
1 a5 1 a3 0 0 a5 0 a3
1 a4 1 a2 1 1 a4 1 a2
0 a3 0 a1 0 0 a3 0 a1
0 a2 0 a0 0 0 a2 0 a0
Second Byte
Bit Addresses a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
a2 a2
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
LDB Load Bit
LDB Examples: (Continued) 1. The carry flag is set and the data value at input pin P1.0 is logic zero. The following instruction clears the carry flag to logic zero. LDB C,P1.0
2. The P1 address is FF1H and the L register contains the value 9H (1001B). The address (memb.7-2) is 111100B and (L.3-2) is 10B. The resulting address is 11110010B or FF2H and P2 is addressed. The bit value (L.1-0) is specified as 01B (bit 1). LD LDB L,#9H C,P1.@L ; P1.@L specifies P2.1 and C P2.1
3. The H register contains the value 2H and FLAG = 20H.3. The address for H is 0010B and for FLAG(3-0) the address is 0000B. The resulting address is 00100000B or 20H. The bit value is 3. Therefore, @H+FLAG = 20H.3. FLAG EQU LD LDB 20H.3 H,#2H C,@H+FLAG ;
C FLAG (20H.3)
4. The following instruction sequence sets the carry flag and the loads the "1" data value to the output pin P2.0, setting it to output mode: SCF LDB P2.0,C ; ; C "1" P2.0 "1"
5. The P1 address is FF1H and L = 9H (1001B). The address (memb.7-2) is 111100B and (L.3-2) is 10B. The resulting address, 11110010B specifies P2. The bit value (L.1-0) is specified as 01B (bit 1). Therefore, P1.@L = P2.1. SCF LD LDB ; L,#9H P1.@L,C ; ; C "1" P1.@L specifies P2.1 P2.1 "1"
6. In this example, H = 2H and FLAG = 20H.3 and the address 20H is specified. Because the bit value is 3, @H+FLAG = 20H.3: FLAG EQU 20H.3 RCF ; LD H,#2H LDB@H+FLAG,C ; C "0" FLAG(20H.3) "0"
NOTE Port pin names used in examples 4 and 5 may vary with different SAM47 devices.
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
LDC Load Code Byte
LDC Operation: dst,src Operand EA,@WX EA,@EA Operation Summary Load code byte from WX to EA Load code byte from EA to EA Bytes 1 1 Cycles 3 3
Description:
This instruction is used to load a byte from program memory into an extended accumulator. The address of the byte fetched is the five highest bit values in the program counter and the contents of an 8-bit working register (either WX or EA). The contents of the source are unaffected. Operand EA,@WX EA,@EA 1 1 1 1 0 0 Binary Code 0 0 1 1 1 0 0 0 0 0 Operation Notation EA [PC13-8 + (WX)] EA [PC13-8 + (EA)]
Examples:
1. The following instructions will load one of four values defined by the define byte (DB) directive to the extended accumulator: LD CALL JPS ORG DB DB DB DB
* * *
EA,#00H DISPLAY MAIN 0500H 66H 77H 88H 99H
DISPLAY LDC RET
EA,@EA
; EA address 0500H = 66H
If the instruction 'LD EA,#01H' is executed in place of 'LD EA,#00H', The content of 0501H (77H) is loaded to the EA register. If 'LD EA,#02H' is executed, the content of address 0502H (88H) is loaded to EA.
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
LDC Load Code Byte
LDC Examples: (Continued) 2. The following instructions will load one of four values defined by the define byte (DB) directive to the extended accumulator: ORG DB DB DB DB
* * *
0500 66H 77H 88H 99H
DISPLAY LD LDC RET
WX,#00H EA,@WX
; EA address 0500H = 66H
If the instruction 'LD WX,#01H' is executed in place of 'LD WX,#00H', then EA address 0501H = 77H. If the instruction 'LD WX,#02H' is executed in place of 'LD WX,#00H', then EA address 0502H = 88H. 3. Normally, the LDC EA, @EA and the LDC EA, @WX instructions reference the table data on the page on which the instruction is located. If, however, the instruction is located at address xxFFH, it will reference table data on the next page. In this example, the upper 4 bits of the address at location 0200H is loaded into register E and the lower 4 bits into register A: 01FDH 01FFH ORG LD LDC 01FDH WX,#00H EA,@WX
; E upper 4 bits of 0200H address ; A lower 4 bits of 0200H address
4. Here is another example of page referencing with the LDC instruction: ORG DB SMB LD LD LDC LD 0100 67H 0 HL,#30H WX,#00H EA,@WX @HL,EA
; Even number ; E upper 4 bits of 0100H address ; A lower 4 bits of 0100H address ; RAM (30H) 7, RAM (31H) 6
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
LDD Load Data Memory and Decrement
LDD Operation: dst Operand A,@HL Operation Summary Load indirect data memory contents to A; decrement register L contents and skip on borrow Bytes 1 Cycles 2+S
Description:
The contents of a data memory location are loaded into the accumulator, and the contents of the register L are decremented by one. If a "borrow" occurs (e.g., if the resulting value in register L is 0FH), the next instruction is skipped. The contents of data memory and the carry flag value are not affected. Operand A,@HL 1 0 0 Binary Code 0 1 0 1 1 Operation Notation A (HL), then L L-1; skip if L = 0FH
Example:
In this example, assume that register pair HL contains 20H and internal RAM location 20H contains the value 0FH: LD LDD JPS JPS HL,#20H A,@HL XXX YYY ; A (HL) and L L-1 ; Skip ; H 2H and L 0FH
The instruction 'JPS XXX' is skipped because a "borrow" occurred after the 'LDD A,@HL' and instruction 'JPS YYY' is executed.
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
LDI Load Data Memory and Increment
LDI Operation: dst,src Operand A,@HL Operation Summary Load indirect data memory to A; increment register L contents and skip on overflow Bytes 1 Cycles 2+S
Description:
The contents of a data memory location are loaded into the accumulator, and the contents of the register L are incremented by one. If an overflow occurs (e.g., if the resulting value in register L is 0H), the next instruction is skipped. The contents of data memory and the carry flag value are not affected. Operand A,@HL 1 0 0 Binary Code 0 1 0 1 0 Operation Notation A (HL), then L L+1; skip if L = 0H
Example:
Assume that register pair HL contains the address 2FH and internal RAM location 2FH contains the value 0FH: LD LDI JPS JPS HL,#2FH A,@HL XXX YYY ; A (HL) and L L+1 ; Skip ; H 2H and L 0H
The instruction 'JPS XXX' is skipped because an overflow occurred after the 'LDI A,@HL' and the instruction 'JPS YYY' is executed.
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
NOP No Operation
NOP Operation: Operand -- Operation Summary No operation Bytes 1 Cycles 1
Description:
No operation is performed by a NOP instruction. It is typically used for timing delays. One NOP causes a 1-cycle delay: with a 1-s cycle time, five NOPs would therefore cause a 5s delay. Program execution continues with the instruction immediately following the NOP. Only the PC is affected. At least three NOP instructions should follow a STOP or IDLE instruction. Operand -- 1 0 1 Binary Code 0 0 0 0 0 Operation Notation No operation
Example:
Three NOP instructions follow the STOP instruction to provide a short interval for clock stabilization before power-down mode is initiated: STOP NOP NOP NOP
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INSTRUCTION SET
OR Logical OR
OR Operation: dst,src Operand A, #im A, @HL EA,RR RRb,EA Operation Summary Logical-OR immediate data to A Logical-OR indirect data memory contents to A Logical-OR double register to EA Logical-OR EA to double register Bytes 2 1 2 2 Cycles 2 1 2 2
Description:
The source operand is logically ORed with the destination operand. The result is stored in the destination. The contents of the source are unaffected. Operand A, #im A, @HL EA,RR RRb,EA 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 1 0 1 0 1 Binary Code 1 0 1 1 0 1 0 1 d3 1 1 1 1 0 1 d2 0 1 r2 1 r2 0 d1 1 0 r1 0 r1 1 d0 0 0 0 0 0 RRb RRb OR EA A A OR (HL) EA EA OR RR Operation Notation A A OR im
Example:
If the accumulator contains the value 0C3H (11000011B) and register pair HL the value 55H (01010101B), the instruction OR EA,@HL
leaves the value 0D7H (11010111B) in the accumulator .
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
POP Pop from Stack
POP Operation: dst Operand RR SB Operation Summary Pop to register pair from stack Pop SMB and SRB values from stack Bytes 1 2 Cycles 1 2
Description:
The contents of the RAM location addressed by the stack pointer is read, and the SP is incremented by two. The value read is then transferred to the variable indicated by the destination operand. Operand RR SB 0 1 0 0 1 1 1 0 1 Binary Code 0 1 0 1 1 0 r2 1 1 r1 0 1 0 1 0 Operation Notation RRL (SP), RRH (SP+1) SP SP+2 (SRB) (SP), SMB (SP+1), SP SP+2
Example:
The SP value is equal to 0EDH, and RAM locations 0EFH through 0EDH contain the values 2H, 3H, and 4H, respectively. The instruction POP HL
leaves the stack pointer set to 0EFH and the data pointer pair HL set to 34H.
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INSTRUCTION SET
PUSH Push onto Stack
PUSH Operation: src Operand RR SB Operation Summary Push register pair onto stack Push SMB and SRB values onto stack Bytes 1 2 Cycles 1 2
Description:
The SP is then decremented by two and the contents of the source operand are copied into the RAM location addressed by the stack pointer, thereby adding a new element to the top of the stack. Operand RR SB 0 1 0 0 1 1 1 0 1 Binary Code 0 1 0 1 1 0 r2 1 1 r1 0 1 1 1 1 Operation Notation (SP-1) RRH, (SP-2) RRL SP SP-2 (SP-1) SMB, (SP-2) SRB; (SP) SP-2
Example:
As an interrupt service routine begins, the stack pointer contains the value 0FAH and the data pointer register pair HL contains the value 20H. The instruction PUSH HL
leaves the stack pointer set to 0F8H and stores the values 2H and 0H in RAM locations 0F9H and 0F8H, respectively.
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
RCF Reset Carry Flag
RCF Operation: Operand -- Operation Summary Reset carry flag to logic zero Bytes 1 Cycles 1
Description:
The carry flag is cleared to logic zero, regardless of its previous value. Operand -- 1 1 1 Binary Code 0 0 1 1 0 Operation Notation C0
Example:
Assuming the carry flag is set to logic one, the instruction RCF resets (clears) the carry flag to logic zero.
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
REF Reference Instruction
REF Operation: dst Operand memc Operation Summary Reference code Bytes 1 Cycles 3*
*
Description:
The REF instruction for a 16K CALL instruction is 4 cycles.
The REF instruction is used to rewrite into 1-byte form, arbitrary 2-byte or 3-byte instructions (or two 1-byte instructions) stored in the REF instruction reference area in program memory. REF reduces the number of program memory accesses for a program. Operand memc t7 t6 t5 Binary Code t4 t3 t2 t1 t0 Operation Notation PC13-0 = memc7-4, memc3-0 <1
TJP and TCALL are 2-byte pseudo-instructions that are used only to specify the reference area: 1. When the reference area is specified by the TJP instruction, memc.7-6 = 00 P11-0 memc.3-0 + (memc + 1) 2. When the reference area is specified by the TCALL instruction, memc.7-6 = 01 (SP-4) (SP-1) (SP-2) PC11-0 SP-3 EMB, ERB, 0, 0 PC11-0 memc.3-0 + (memc + 1) SP SP-4 When the reference area is specified by any other instruction, the 'memc' and 'memc + 1' instructions are executed. Instructions referenced by REF occupy two bytes of memory space (for two 1-byte instructions or one 2-byte instruction) and must be written as an even number from 0020H to 007FH in ROM. In addition, the destination address of the TJP and TCALL instructions must be located with the 3FFFH address. TJP and TCALL are reference instructions for JP/JPS and CALL/CALLS. If the instruction following a REF is subject to the 'redundancy effect', the redundant instruction is skipped. If, however, the REF follows a redundant instruction, it is executed. On the other hand, the binary code of a REF instruction is 1 byte. The upper four bits become the higher address bits of the referenced instruction, and the lower four bits of the referenced instruction ( x 1/2) becomes the lower address, producing a total of 8 bits or 1 byte (see Example 3 below).
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
REF Reference Instruction
REF Examples: (Continued) 1. Instructions can be executed efficiently using REF, as shown in the following example: AAA BBB CCC DDD ORG 0020H LD HL,#00H LD EA,#FFH TCALL SUB1 TJP SUB2 * * * ORG 0080H REF AAA REF BBB REF CCC REF DDD
; ; ; ;
LD LD CALL JP
HL,#00H EA,#FFH SUB1 SUB2
2. The following example shows how the REF instruction is executed in relation to LD instructions that have a 'redundancy effect': AAA ORG LD
* * *
0020H EA,#40H
ORG LD REF
* * *
0100H EA,#30H AAA
; Not skipped
REF LD SRB
AAA EA,#50H 2
; Skipped
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
REF Reference Instruction
REF Examples: (Concluded) 3. In this example the binary code of 'REF A1' at locations 20H-21H is 20H, for 'REF A2' at locations 22H-23H, it is 21H, and for 'REF A3' at 24H-25H, the binary code is 22H : Opcode ; 83 83 83 83 83 83 83 83 83 41 01 Symbol Instruction ORG 00 03 05 10 26 08 0F F0 67 0B 0D A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 LD LD LD LD LD LD LD LD LD TCALL TJP
* * *
0020H HL,#00H HL,#03H HL,#05H HL,#10H HL,#26H HL,#08H HL,#0FH HL,#0F0H HL,#067H SUB1 SUB2
ORG ; 20 21 22 23 24 25 26 27 30 31 32 REF REF REF REF REF REF REF REF REF REF REF
0100H A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 ; ; ; ; ; ; ; ; ; ; ; LD LD LD LD LD LD LD LD LD CALL JP HL,#00H HL,#03H HL,#05H HL,#10H HL,#26H HL,#08H HL,#0FH HL,#0F0H HL,#067H SUB1 SUB2
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
RET Return from Subroutine
RET Operation: Operand -- Operation Summary Return from subroutine Bytes 1 Cycles 3
Description:
RET pops the PC values successively from the stack, incrementing the stack pointer by six. Program execution continues from the resulting address, generally the instruction immediately following a CALL or CALLS. Operand -- 1 1 0 Binary Code 0 0 1 0 1 Operation Notation PC13-8 (SP+1) (SP) PC7-0 (SP+2) (SP+3) PSW EMB,ERB SP SP+6
Example:
The stack pointer contains the value 0FAH. RAM locations 0FAH, 0FBH, 0FCH, and and 0FDH contain 1H, 0H, 5H, and 2H, respectively. The instruction RET leaves the stack pointer with the new value of 00H and program execution continues from location 0125H. During a return from subroutine, PC values are popped from stack locations as follows: SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 0 0 0 PC11 - PC8 0 PC13 - PC12 PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
RRC Rotate Accumulator Right through Carry
RRC Operation: A Operand A Operation Summary Rotate right through carry bit Bytes 1 Cycles 1
Description:
The four bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag and the original carry value moves into the bit 3 accumulator position.
3 C
0
Operand A 1 0 0
Binary Code 0 1 0 0 0
Operation Notation C A.0, A3 C A.n-1 A.n (n = 1, 2, 3)
Example:
The accumulator contains the value 5H (0101B) and the carry flag is cleared to logic zero. The instruction RRC A
leaves the accumulator with the value 2H (0010B) and the carry flag is set to logic one.
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KS57C0502/C0504/P0504 MICROCONTROLLER
SBC Subtract with Carry
SBC Operation: dst,src Operand A,@HL EA,RR RRb,EA Operation Summary Subtract indirect data memory from A with carry Subtract register pair (RR) from EA with carry Subtract EA from register pair (RRb) with carry Bytes 1 2 2 Cycles 1 2 2
Description:
SBC subtracts the source and carry flag value from the destination operand, leaving the result in the destination. SBC sets the carry flag if a borrow is needed for the most significant bit; otherwise it clears the carry flag. The contents of the source are unaffected. If the carry flag was set before the SBC instruction was executed, a borrow was needed for the previous step in multiple precision subtraction. In this case, the carry bit is subtracted from the destination along with the source operand. Operand A,@HL EA,RR RRb,EA 0 1 1 1 1 0 1 1 1 1 1 0 0 0 0 Binary Code 1 1 0 1 0 1 1 1 1 0 1 1 r2 1 r2 0 0 r1 0 r1 0 0 0 0 0 C,RRb RRb - EA - C Operation Notation C,A A - (HL) - C C, EA EA -RR - C
Examples:
1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is set to "1": SCF SBC JPS EA,HL XXX ; C "1" ; EA 0C3H - 0AAH - 1H, C "0" ; Jump to XXX; no skip after SBC
2. If the extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is cleared to "0": RCF SBC JPS EA,HL XXX ; C "0" ; EA 0C3H - 0AAH - 0H = 19H, C "0" ; Jump to XXX; no skip after SBC
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
SBC Subtract with Carry
SBC Examples: (Continued) 3. If SBC A,@HL is followed by an ADS A,#im, the SBC skips on 'no borrow' to the instruction immediately after the ADS. An 'ADS A,#im' instruction immediately after the 'SBC A,@HL' instruction does not skip even if an overflow occurs. This function is useful for decimal adjustment operations. a. 8 - 6 decimal addition (the contents of the address specified by the HL register is 6H): RCF LD SBC ADS JPS A,#8H A,@HL A,#0AH XXX ; ; ; ; C "0" A 8H A 8H - 6H - C(0) = 2H, C "0" Skip this instruction because no borrow after SBC result
b. 3 - 4 decimal addition (the contents of the address specified by the HL register is 4H): RCF LD SBC ADS A,#3H A,@HL A,#0AH ; ; ; ; ; ; C "0" A 3H A 3H - 4H - C(0) = 0FH, C "1" No skip. A 0FH + 0AH = 9H (The skip function of 'ADS A,#im' is inhibited after a 'SBC A,@HL' instruction even if an overflow occurs.)
JPS
XXX
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
SBS Subtract
SBS Operation: dst,src Operand A,@HL EA,RR RRb,EA Operation Summary Subtract indirect data memory from A; skip on borrow Subtract register pair (RR) from EA; skip on borrow Subtract EA from register pair (RRb); skip on borrow Bytes 1 2 2 Cycles 1+S 2+S 2+S
Description:
The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. A skip is executed if a borrow occurs. The value of the carry flag is not affected. Operand A,@HL EA,RR RRb,EA 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 Binary Code 1 1 1 1 1 1 1 1 1 0 1 1 r2 1 r2 0 0 r1 0 r1 1 0 0 0 0 RRb RRb - EA; skip on borrow Operation Notation A A - (HL); skip on borrow EA EA - RR; skip on borrow
Examples:
1. The accumulator contains the value 0C3H, register pair HL contains the value 0C7H, and the carry flag is cleared to logic zero: RCF SBS EA,HL ; ; ; ; ; ; C "0" EA 0C3H - 0C7H, C "0" SBS instruction skips on borrow, but carry flag value is not affected Skip because a borrow occurred Jump to YYY is executed
JPS JPS
XXX YYY
2. The accumulator contains the value 0AFH, register pair HL contains the value 0AAH, and the carry flag is set to logic one: SCF SBS JPS EA,HL XXX ; ; ; ; C "1" EA 0AFH - 0AAH, C "1" Jump to XXX JPS was not skipped because no "borrow" occurred after SBS
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
SCF Set Carry Flag
SCF Operation: Operand -- Operation Summary Set carry flag to logic one Bytes 1 Cycles 1
Description:
The SCF instruction sets the carry flag to logic one, regardless of its previous value. Operand -- 1 1 1 Binary Code 0 0 1 1 1 Operation Notation C1
Example:
If the carry flag is cleared to logic zero, the instruction SCF sets the carry flag to logic one.
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
SMB Select Memory Bank
SMB Operation: n Operand n Operation Summary Select memory bank Bytes 2 Cycles 2
Description:
The SMB instruction sets the upper four bits of a 12-bit data memory address to select a specific memory bank. The constants 0, 1, and 15 are usually used as the SMB operand to select the corresponding memory bank. All references to data memory addresses fall within the following address ranges: Please note that because data memory spaces differ for various devices in the SAM47 product family, the 'n' value of the SMB instruction will also vary. Addresses 000H-01FH 020H-0FFH 100H-1DFH 1E0H-1FFH F80H-FFFH Register Areas Working registers Stack and general-purpose registers General-purpose registers Display registers I/O-mapped hardware registers 15 15 1 1 Bank 0 SMB 0
The enable memory bank (EMB) flag must always be set to "1" in order for the SMB instruction to execute successfully for memory banks 0, 1, and 15. Format n 1 0 1 1 0 0 Binary Code 1 0 1 d3 1 d2 0 d1 1 d0 Operation Notation SMB n (n = 0, 1, 15)
Example:
If the EMB flag is set, the instruction SMB 0
selects the data memory address range for bank 0 (000H-0FFH) as the working memory bank.
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
SRB Select Register Bank
SRB Operation: n Operand n Operation Summary Select register bank Bytes 2 Cycles 2
Description:
The SRB instruction selects one of four register banks in the working register memory area. The constant value used with SRB is 0, 1, 2, or 3. The following table shows the effect of SRB settings: ERB Setting 3 0 1 0 0 SRB Settings 2 0 0 1 x 0 0 1 1
NOTE: 'x' means don't care.
Selected Register Bank 0 x 0 1 0 1 Always set to bank 0 Bank 0 Bank 1 Bank 2 Bank 3
The enable register bank flag (ERB) must always be set for the SRB instruction to execute successfully for register banks 0, 1, 2, and 3. In addition, if the ERB value is logic zero, register bank 0 is always selected, regardless of the SRB value. Operand n 1 0 1 1 0 0 Binary Code 1 1 1 0 1 0 0 d1 1 d0 Operation Notation SRB n (n = 0, 1, 2, 3)
Example:
If the ERB flag is set, the instruction SRB 3
selects register bank 3 (018H-01FH) as the working memory register bank.
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
SRET Return from Subroutine and Skip
SRET Operation: Operand -- Operation Summary Return from subroutine and skip Bytes 1 Cycles 3+S
Description:
SRET is normally used to return to the previously executing procedure at the end of a subroutine that was initiated by a CALL or CALLS instruction. SRET skips the resulting address, which is generally the instruction immediately after the point at which the subroutine was called. Then, program execution continues from the resulting address and the contents of the location addressed by the stack pointer are popped into the program counter. Operand -- 1 1 1 Binary Code 0 0 1 0 1 Operation Notation PC13-8 (SP + 1) (SP) PC7-0 (SP + 3) (SP + 2) EMB,ERB (SP + 5) (SP + 4) SP SP + 6
Example:
If the stack pointer contains the value 0FAH and RAM locations 0FAH, 0FBH, 0FCH, and 0FDH contain the values 1H, 0H, 5H, and 2H, respectively, the instruction SRET leaves the stack pointer with the value 00H and the program returns to continue execution at location 0125H. During a return from subroutine, data is popped from the stack to the PC as follows: SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 0 0 0 PC11 - PC8 0 PC13 - PC12 PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
STOP Stop Operation
STOP Operation: Operand -- Operation Summary Engage CPU stop mode Bytes 2 Cycles 2
Description:
The STOP instruction stops the system clock by setting bit 3 of the power control register (PCON) to logic one. When STOP executes, all system operations are halted with the exception of some peripheral hardware with special power-down mode operating conditions. In application programs, a STOP instruction should be immediately followed by at least three NOP instructions. This ensures an adequate time interval for the clock to stabilize before the next instruction is executed. Operand -- 1 1 1 0 1 1 Binary Code 1 1 1 0 1 0 1 1 1 1 Operation Notation PCON.3 1
Example:
Given that bit 3 of the PCON register is cleared to logic zero, and all systems are operational, the instruction sequence STOP NOP NOP NOP sets bit 3 of the PCON register to logic one, stopping all controller operations (with the exception of some peripheral hardware). The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed.
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
VENT Load EMB, ERB, and Vector Address
VENTn Operation: dst Operand EMB (0,1) ERB (0,1) ADR Operation Summary Load enable memory bank flag (EMB) and the enable register bank flag (ERB) and program counter to vector address, then branch to the corresponding location. Bytes 2 Cycles 2
Description:
The VENT instruction loads the contents of the enable memory bank flag (EMB) and enable register bank flag (ERB) into the respective vector addresses. It then points the interrupt service routine to the corresponding branching locations. The program counter is loaded automatically with the respective vector addresses which indicate the starting address of the respective vector interrupt service routines. The EMB and ERB flags should be modified using VENT before the vector interrupts are acknowledged. Then, when an interrupt is generated, the EMB and ERB values of the previous routine are automatically pushed onto the stack and then popped back when the routine is completed. After the return from interrupt (IRET) you do not need to set the EMB and ERB values again. Instead, use BITR and BITS to clear these values in your program routine. The starting addresses for vector interrupts and reset operations are pointed to by the VENTn instruction. These addresses must be stored in ROM locations 0000H-3FFFH. Generally, the VENTn instructions are coded starting at location 0000H. The format for VENT instructions is as follows: VENTn d1,d2,ADDR EMB d1 ("0" or "1") ERB d2 ("0" or "1") PC ADDR (address to branch n = device-specific module address code (n = 0-n) Operand EMB (0,1) ERB (0,1) ADR E M B E R B Binary Code a13 a12 a11 a10 a9 a8 Operation Notation ROM (2 x n) 7-6 EMB, ERB ROM (2 x n) 5-4 0, PC13, PC12 ROM (2 x n) 3-0 PC12-8 ROM (2 x n + 1) 7-0 PC7-0 (n = 0, 1, 2, 3, 4, 5, 6, 7)
a7
a6
a5
a4
a3
a2
a1
a0
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
VENT Load EMB, ERB, and Vector Address
VENTn Example: (Continued) The instruction sequence ORG VENT0 VENT1 VENT2 VENT3 VENT4 VENT5 0000H 1,0,RESET 0,1,INTB 0,1,INT0 0,1,INTS 0,1,INTT0 0,1,INTT1
causes the program sequence to branch to the RESET routine labeled 'RESET,' setting EMB to "1" and ERB to "0" when RESET is activated. When a basic timer interrupt is generated, VENT1 causes the program to branch to the basic timer's interrupt service routine, INTB, and to set the EMB value to "0" and the ERB value to "1". VENT2 then branches to INT0, VENT3 to INTS, and so on, setting the appropriate EMB and ERB values.
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
XCH Exchange A or EA with Nibble or Byte
XCH Operation: dst,src Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL Operation Summary Exchange A and data memory contents Exchange A and register (Ra) contents Exchange A and indirect data memory Exchange EA and direct data memory contents Exchange EA and register pair (RRb) contents Exchange EA and indirect data memory contents Bytes 2 1 1 2 2 2 Cycles 2 1 1 2 2 2
Description:
The instruction XCH loads the accumulator with the contents of the indicated destination variable and writes the original contents of the accumulator to the source. Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL 0 a7 0 0 1 a7 1 1 1 0 1 a6 1 1 1 a6 1 1 1 0 1 a5 1 1 0 a5 0 1 0 0 Binary Code 1 a4 0 1 0 a4 1 0 1 0 1 a3 1 1 1 a3 1 0 1 0 0 a2 r2 i2 1 a2 1 r2 1 0 0 a1 r1 i1 1 a1 0 r1 0 0 1 a0 r0 i0 1 a0 0 0 0 1 A (HL), E (HL + 1) EA RRb A Ra A (RRa) A DA,E DA + 1 Operation Notation A DA
Example:
Double register HL contains the address 20H. The accumulator contains the value 3FH (00111111B) and internal RAM location 20H the value 75H (01110101B). The instruction XCH EA,@HL
leaves RAM location 20H with the value 3FH (00111111B) and the extended accumulator with the value 75H (01110101B).
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
XCHD Exchange and Decrement
XCHD Operation: dst,src Operand A,@HL Operation Summary Exchange A and data memory contents; decrement contents of register L and skip on borrow Bytes 1 Cycles 2+S
Description:
The instruction XCHD exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then decrements the contents of register L. If the content of register L is 0FH, the next instruction is skipped. The value of the carry flag is not affected. Operand A,@HL 0 1 1 Binary Code 1 1 0 1 1 Operation Notation A (HL), then L L-1; skip if L = 0FH
Example:
Register pair HL contains the address 20H and internal RAM location 20H contains the value 0FH: LD LD XCHD JPS JPS XCHD
* * *
YYY
HL,#20H A,#0H A,@HL XXX YYY A,@HL
; ; ; ;
A 0FH and L L - 1, (HL) "0" Skipped because a borrow occurred H 2H, L 0FH (2FH) 0FH, A (2FH), L L - 1 = 0EH
The 'JPS YYY' instruction is executed because a skip occurs after the XCHD instruction.
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
XCHI Exchange and Increment
XCHI Operation: dst,src Operand A,@HL Operation Summary Exchange A and data memory contents; increment contents of register L and skip on overflow Bytes 1 Cycles 2+S
Description:
The instruction XCHI exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then increments the contents of register L. If the content of register L is 0H, a skip is executed. The value of the carry flag is not affected. Operand A,@HL 0 1 1 Binary Code 1 1 0 1 0 Operation Notation A (HL), then L L+1; skip if L = 0H
Example:
Register pair HL contains the address 2FH and internal RAM location 2FH contains 0FH: LD LD XCHI JPS JPS XCHI
* * *
YYY
HL,#2FH A,#0H A,@HL XXX YYY A,@HL
; ; ; ;
A 0FH and L L + 1 = 0, (HL) "0" Skipped because an overflow occurred H 2H, L 0H (20H) 0FH, A (20H), L L + 1 = 1H
The 'JPS YYY' instruction is executed because a skip occurs after the XCHI instruction.
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KS57C0502/C0504/P0504 MICROCONTROLLER
INSTRUCTION SET
XOR Logical Exclusive OR
XOR Operation: dst,src Operand A,#im A,@HL EA,RR RRb,EA Operation Summary Exclusive-OR immediate data to A Exclusive-OR indirect data memory to A Exclusive-OR register pair (RR) to EA Exclusive-OR register pair (RRb) to EA Bytes 2 1 2 2 Cycles 2 1 2 2
Description:
XOR performs a bitwise logical XOR operation between the source and destination variables and stores the result in the destination. The source contents are unaffected. Operand A,#im A,@HL EA,RR RRb,EA 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 1 0 1 0 1 Binary Code 1 1 1 1 1 1 1 1 d3 1 1 1 1 0 1 d2 0 1 r2 1 r2 0 d1 1 0 r1 0 r1 1 d0 1 0 0 0 0 RRb RRb XOR EA A A XOR (HL) EA EA XOR (RR) Operation Notation A A XOR im
Example:
If the extended accumulator contains 0C3H (11000011B) and register pair HL contains 55H (01010101B), the instruction XOR EA,HL
leaves the value 96H (10010110B) in the extended accumulator.
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INSTRUCTION SET
KS57C0502/C0504/P0504 MICROCONTROLLER
NOTES
5-94
Oscillator Circuits Interrupts Power-Down
RESET
I/O Ports Timers and Timer/Counter Comparator Serial I/O Interface Electrical Data Mechanical Data KS57P0504 OTP Development Tools
KS57C0502/C0504/P0504 MICROCONTROLLER
OSCILLATOR CIRCUIT
6
OSCILLATOR CIRCUITS
OVERVIEW The KS57C0502/C0504 has a system clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these on-chip circuits. Specifically, a clock is required by the following peripheral modules: -- Basic timer -- Timer/counter 0 -- Watch timer -- Serial I/O interface -- Clock output circuit The system clock frequency can be divided by 4, 8, or 64. By manipulating PCON bits 1 and 0, you can select one of the following frequencies as the cpu clock. fx fx fx 4 , 8 , 64 When the PCON register is cleared to zero after RESET, the normal CPU operating mode is enabled, a system clock of fx/64 is selected. Bits 3 and 2 of the PCON register can be manipulated by a STOP or IDLE instruction to engage stop or idle power-down mode.
6-1
OSCILLATOR CIRCUIT
KS57C0502/C0504/P0504 MICROCONTROLLER
SYSTEM OSCILLATOR CIRCUIT
fx
Xin
Xout FREQUENCY DIVIDING CIRCUIT OSCILLATOR STOP
1/2 1/16
WATCH TIMER BASIC TIMER TIMER/COUNTER 0 CLOCK OUTPUT CIRCIT COMPARATOR
SELECTOR
1/4
CPU CLOCK
CPU STOP SIGNAL ( IDLE MODE) PCON.0 PCON.1 IDLE STOP PCON.2 PCON.3 OSCILLATOR CONTROL CIRCUIT WAIT RELEASE SIGNAL INTERNAL RESET SIGNAL POWER-DOWN RELEASE SIGNAL
PCON.3,2 CLEAR
Figure 6-1. Clock Circuit Diagram
6-2
KS57C0502/C0504/P0504 MICROCONTROLLER
OSCILLATOR CIRCUIT
SYSTEM OSCILLATOR CIRCUITS
Xin
Xin
Xout Xout
Figure 6-2. Crystal/Ceramic Oscillator
Figure 6-3. External Clock
6-3
OSCILLATOR CIRCUIT
KS57C0502/C0504/P0504 MICROCONTROLLER
POWER CONTROL REGISTER (PCON) The power control register, PCON, is a 4-bit register that is used to select the CPU clock frequency and to control CPU operating and power-down modes. PCON is mapped to RAM address FB3H and can be addressed directly by 4-bit write instructions or by the instructions IDLE and STOP. FB3H PCON.3 PCON.2 PCON.1 PCON.0
PCON bits 3 and 2 are controlled by the STOP and IDLE instructions to engage the idle and stop power-down modes. Idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag (EMB). PCON bits 1 and 0 are used to select a specific system clock frequency. RESET sets PCON register values to logic zero. PCON.1 and PCON.0 divide the frequency (fx) by 64, 8, and 4. PCON.3 and PCON.2 enable normal CPU operating mode. Table 6-1. Power Control Register (PCON) Organization PCON Bit Settings PCON.3 0 0 1 PCON.2 0 1 0 Normal CPU operating mode Idle power-down mode Stop power-down mode Resulting CPU Clock Frequency fx/64 fx/8 fx/4 Resulting CPU Operating Mode
PCON Bit Settings PCON.1 0 1 1 PCON.0 0 0 1
+ PROGRAMMING TIP -- Setting the CPU Clock
To set the CPU clock to 0.95 s at 4.19 MHz: BITS SMB LD LD EMB 15 A,#3H PCON,A
6-4
KS57C0502/C0504/P0504 MICROCONTROLLER
OSCILLATOR CIRCUIT
INSTRUCTION CYCLE TIMES The unit of time that equals one machine cycle varies depending on how the oscillator clock signal is divided (by 4, 8, or 64). Table 6-2 shows corresponding cycle times in microseconds. Table 6-2. Instruction Cycle Times for CPU Clock Rates Selected CPU Clock fx/64 fx/8 fx/4 Resulting Frequency 65.5 kHz 524.0 kHz 1.05 MHz fx = 4.19 MHz Oscillation Source Cycle Time (sec) 15.3 1.91 0.95
CLOCK OUTPUT MODE REGISTER (CLMOD) The clock output mode register, CLMOD, is a 4-bit register that is used to enable or disable clock output to the CLO pin and to select the CPU clock source and frequency. CLMOD is mapped to RAM address FD0H and is addressable by 4-bit write instructions only. FD0H CLMOD.3 "0" CLMOD.1 CLMOD.0
RESET clears CLMOD to logic zero, which automatically selects the CPU clock as the clock source (without initiating clock oscillation), and disables clock output. CLMOD.3 is the enable/disable clock output control bit; CLMOD.1 and CLMOD.0 are used to select one of four possible clock sources and frequencies: normal CPU clock, fx/8, fx/16, or fx/64.
Table 6-3. Clock Output Mode Register (CLMOD) Organization CLMOD Bit Settings CLMOD.1 0 0 1 1 CLMOD.3 0 1 Clock output is disabled Clock output is enabled CLMOD.0 0 1 0 1 Clock Source CPU clock (fx/4, fx/8, fx/64) fx/8 fx/16 fx/64 Result of CLMOD.3 Setting Resulting Clock Output Frequency 1.05 MHz, 524 kHz, 65.5 kHz 524 kHz 262 kHz 65.5 kHz
NOTE: Frequencies assume that fx = 4.19 MHz.
6-5
OSCILLATOR CIRCUIT
KS57C0502/C0504/P0504 MICROCONTROLLER
CLOCK OUTPUT CIRCUIT The clock output circuit, used to output clock pulses to the CLO pin, has the following components: -- 4-bit clock output mode register (CLMOD) -- Clock selector -- Output latch -- Port mode flag -- CLO output pin (P3.2)
CLMOD.3 CLMOD.2 4 CLMOD.1 CLMOD.0 CLOCK SELECTOR P3.2 OUTPUT LATCH PM3.2
CLO
CLOCKS (fx/8, fx/16, fx/64, CPU clock)
Figure 6-4. CLO Output Pin Circuit Diagram
CLOCK OUTPUT PROCEDURE To output clock pulses to the CLO pin, follow this general procedure: 1. Disable clock output by clearing CLMOD.3 to logic zero. 2. Set the clock output frequency (CLMOD.1, CLMOD.0). 3. Load a "0" to the output latch of the CLO pin (P3.2). 4. Set the P3.2 mode flag (PM3.2) to output mode. 5. Enable clock output by setting CLMOD.3 to logic one.
+ PROGRAMMING TIP -- CPU Clock Output to the CLO Pin
To output the CPU clock to the CLO pin: BITS SMB LD LD BITR LD LD EMB 15 EA,#40H PMG1,EA P3.2 A,#9H CLMOD,A ; Or BITR EMB P3.2 Output mode Clear P3.2 output latch
; ;
6-6
KS57C0502/C0504/P0504 MICROCONTROLLER
INTERRUPTS
7
-- -- --
INTERRUPTS
OVERVIEW KS57C0502/C0504 microcontrollers process three types of interrupts: Internal interrupts generated by on-chip processes External interrupts generated by external peripheral devices Quasi-interrupts used for edge detection and clock sources
Table 7-1. Interrupts and Corresponding I/O Pin(s) Interrupt Type External Interrupts Internal Interrupts Quasi-interrupts Interrupt Name INT0, INT1 INTB, INTT0, INTS INTK INTW The interrupt control circuit has four functional components: -- Interrupt enable flags (IEx) -- Interrupt request flags (IRQx) -- Interrupt priority registers (IME and IPR) -- Power-down release signal circuit Vectored Interrupts Interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software. A vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt, are enabled (set to logic one): -- Interrupt enable flag (IEx) -- Interrupt master enable flag (IME) -- Interrupt request flag (IRQx) -- Interrupt status flags (IS0, IS1) -- Interrupt priority register (IPR) If all conditions are satisfied, the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address. I/O Port Pin(s) P1.0, P1.1 Not applicable P6.0-P6.2 (KS0-KS2) Not applicable
7-1
INTERRUPTS
KS57C0502/C0504/P0504 MICROCONTROLLER
Vectored Interrupts (Continued) EMB and ERB flags for RAM memory and register banks are stored in the vector address area of the ROM during interrupt service routines. The flags are stored at the beginning of the program with the VENT instruction. Enable flag values are saved during the main routine, as well as during service routines. Any changes you make to enable flag values during a service routine are not stored in the vector address. When an interrupt occurs, the enable flag values before the interrupt is initiated are saved along with the program status word (PSW), and the enable flag values for the interrupt is fetched from the respective vector address. Then, if required, you can modify the enable flags during the interrupt service routine. When the interrupt service routine is returned to the main routine by the IRET instruction, however, the original values saved in the stack are restored and the main program continues program execution with these values. Software-Generated Interrupts To generate an interrupt request from software, the program manipulates the appropriate IRQx flag. When the interrupt request value in the IRQx flag is set, it is retained until all other conditions for the interrupt have been met, and the service routine can be initiated. Multiple Interrupts By manipulating the two interrupt status flags (IS0 and IS1), you can control service routine initialization and thereby process multiple interrupts simultaneously. Power-Down Mode Release An interrupt (with the exception of INT0) can be used to release power-down mode (stop or idle). Interrupts for power-down mode release are initiated by setting the corresponding interrupt enable flag. Even if the IME flag is cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag has been set. In such cases, the interrupt routine will not be executed since IME = "0".
7-2
KS57C0502/C0504/P0504 MICROCONTROLLER
INTERRUPTS
Interrupt is generated (INT xx)
Request flag (IRQx) <-- 1
IEx = 1? YES
NO
Retain value until IEx = 1
Generate corresponding vector interrupt and release power-down mode
IME = 1? YES YES IS1,0 = 0,0? NO IS1,0 = 0,1 ? YES High-priority interrupt? YES IS1,0 = 0,1 IS1,0 = 1,0
NO
Retain value until IME = 1
Retain value until interrupt service routine is completed NO
NO
Store contents of PC and PSW in the stack area; set PC contents to corresponding vector address
Reset corresponding IRQx flag
Jump to interrupt start address
Figure 7-1. Interrupt Execution Flowchart
7-3
INTERRUPTS
KS57C0502/C0504/P0504 MICROCONTROLLER
IMOD1
IMOD0
IEK
IEW
IET0
IES
IE1
IE0
IEB
INTB INT0 INT1
IRQB IRQ0 IRQ1
# @
@
INTS INTT0 INTW INTK (KS0-KS2) IMODK
IRQS IRQT0 IRQW IRQK
POWER-DOWN MODE RELEASE SIGNAL
IME
IPR
INTERRUPT CONTROL UNIT
IS1 IS0
# = Noise filtering circuit @ = Edge detection circuit
VECTOR INTERRUPT GENERATOR
Figure 7-2. Interrupt Control Circuit Diagram
7-4
KS57C0502/C0504/P0504 MICROCONTROLLER
INTERRUPTS
MULTIPLE INTERRUPTS The interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all interrupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service routine for a lower-priority request is accepted during the execution of a higher priority routine. Two-Level Interrupt Handling Two-level interrupt handling is the standard method for processing multiple interrupts. When the IS1 and IS0 bits of the PSW (FB0H.3 and FB0H.2, respectively) are both logic zero, program execution mode is normal and all interrupt requests are serviced. See Figure 7-3. Whenever an interrupt request is accepted, IS1 and IS0 are incremented by one ("0" "1" or "1" "0"), and the values are stored in the stack along with the other PSW bits. After the interrupt routine has been serviced, the modified IS1 and IS0 values are automatically restored from the stack by an IRET instruction. IS0 and IS1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable memory bank flag (EMB). Before you can modify an interrupt service flag, however, you must first disable interrupt processing with a DI instruction. When you set IS1 to "0" and IS0 to "1", you inhibit all interrupt service routines except for the highest priority interrupt currently defined by the interrupt priority register (IPR).
NORMAL PROGRAM PROCESSING (STATUS 0) INT DISABLE SET IPR INT ENABLE LOW OR HIGH LEVEL INTERRUPT GENERATED
HIGH OR LOW LEVEL INTERRUPT PROCESSING (STATUS 1) HIGH LEVEL INTERRUPT PROCESSING (STATUS 2)
HIGH-LEVEL INTERRUPT GENERATED
Figure 7-3. Two-Level Interrupt Handling Multi-Level Interrupt Handling With multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority interrupt is being serviced. This is done by manipulating the interrupt status flags, IS0 and IS1. See Figure 7-4. When an interrupt is requested during normal program execution, the interrupt status flags IS0 and IS1 are set to "0" and "1", respectively. This setting allows only highest-priority interrupts to be serviced. When a high-priority request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority level can be serviced. In this way, the high-priority and low-priority requests will be serviced in parallel.
7-5
INTERRUPTS
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 7-2. IS1 and IS0 Function Process Status 0 1 2 -- Before INT IS1 0 0 1 1 IS0 0 1 0 1 All interrupt requests are serviced. Only high-priority interrupts as determined by the current settings in the IPR register are serviced. No additional interrupt requests will be serviced. Value undefined Effect of ISx Bit Setting After INT ACK IS1 0 1 -- -- IS0 1 0 -- --
NORMAL PROGRAM PROCESSING (STATUS 0) INT DISABLE SET IPR INT ENABLE LOW OR HIGH LEVEL INTERRUPT GENERATED MODIFY STATUS INT ENABLE LOW OR HIGH LEVEL INTERRUPT GENERATED INT DISABLE
SINGLE INTERRUPT 2-LEVEL INTERRUPT STATUS 1 3-LEVEL INTERRUPT
STATUS 0 HIGH-LEVEL INTERRUPT STATUS 1 STATUS 2 GENERATED
STATUS 0
Figure 7-4. Multiple-Level Interrupt Handling
7-6
KS57C0502/C0504/P0504 MICROCONTROLLER
INTERRUPTS
INTERRUPT PRIORITY REGISTER (IPR) The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. The IPR is mapped to RAM address FB2H, and its reset value is logic zero. Before the IPR can be modified by 4-bit write instructions, all interrupts must first be disabled by a DI instruction. FB2H IME IPR.2 IPR.1 IPR.0
By manipulating the IPR settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. Interrupt INTB INT0 INT1 INTS INTT0 Default Priority 1 2 3 4 5
The MSB of the IPR, the interrupt master enable flag (IME), enables and disables all interrupt processing. Even if an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the IME flag is set to logic one. The IME flag is mapped to FB2H.3 and can be directly manipulated by EI and DI instructions, regardless of the current enable memory bank (EMB) value. Table 7-4. Interrupt Priority Register Settings IPR.2 0 0 0 0 1 1 IPR.1 0 0 1 1 0 0 IPR.0 0 1 0 1 0 1 Result of IPR Bit Setting Process all interrupt requests at low priority. Process INTB interrupt only. Process INT0 interrupts only. Process INT1 interrupts only. Process INTS interrupts only. Process INTT0 interrupts only.
NOTE: When all interrupts are low priority (the lower three bits of the IPR register are logic zero), the interrupt generated first will become high priority. Therefore, the first generated interrupt cannot be superceded by any other interrupt. If two or more interrupt requests are received simultaneously, the priority level is determined according to the standard interrupt priorities in Table 7.4 (e.g., the default priority assigned by hardware when the lower three IPR bits = "0"). In this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. Then, when the high-priority interrupt is returned from its service routine by an IRET instruction, the inhibited interrupt service routine is started.
7-7
INTERRUPTS
KS57C0502/C0504/P0504 MICROCONTROLLER
+ PROGRAMMING TIP -- Setting the INT Interrupt Priority
Set the INT1 interrupt to high priority: BITS SMB DI LD LD EI EMB 15 ; A,#3H IPR,A ;
IPR.3 (IME) 0 IPR.3 (IME) 1
EXTERNAL INTERRUPT MODE REGISTERS (IMOD0, IMOD1) The following components are used to process external interrupts at the INT0 and INT1 pin: -- Noise filtering circuit for INT0 -- Edge detection circuit -- Two mode registers, IMOD0 and IMOD1 The mode registers are used to control the triggering edge of the input signal. IMOD settings let you choose either the rising or falling edge of the incoming signal at the INT0 and INT1 pins as the interrupt request trigger. FB4H FB5H IMOD0.3 "0" "0" "0" IMOD0.1 "0" IMOD0.0 IMOD1.0
IMOD0 and IMOD1 bits are mapped to RAM addresses FB4H (IMOD0) and FB5H (IMOD1), and are addressable by 4-bit write instructions. RESET clears all IMOD values to logic zero, selecting rising edges as the trigger for incoming interrupt requests. Table 7-5. IMOD0 and IMOD1 Register Organization IMOD0 IMOD0.3 0 1 0 0 1 1 IMOD1 0 0 0 0 1 0 1 IMOD1.0 0 1 0 IMOD0.1 IMOD0.0 Effect of IMOD0 Settings Select CPU clock for sampling Select fx/64 sampling clock Rising edge detection Falling edge detection Both rising and falling edge detection IRQ0 flag cannot be set to "1" Effect of IMOD1 Settings Rising edge detection Falling edge detection
7-8
KS57C0502/C0504/P0504 MICROCONTROLLER
INTERRUPTS
EXTERNAL INTERRUPT 0 and 1 MODE REGISTERS (Continued) When a sampling clock rate of fx/64 is used for INT0, an interrupt request flag must be cleared before 16 machine cycles have elapsed. Since the INT0 pin has a clock-driven noise filtering circuit built into it, please take the following precautions when you use it: -- To trigger an interrupt, the input signal width at INT0 must be at least two times wider than the pulse width of the clock selected by IMOD0. This is true even when the INT0 pin is used for general-purpose input. -- Since the INT0 input sampling clock does not operate during stop or idle mode, you cannot use INT0 to release power-down mode.
INT0
NOISE FILTER
EDGE DETECTION
IRQ0
CLOCK SELECTOR
IRQ1
CPU clock INT1
fx/64 EDGE DETECTION
IMOD0 P1.1 P1.0
IMOD1
Figure 7-5. Circuit Diagram for INT0 and INT1 Pins When modifying the IMOD0 and IMOD1 registers, it is possible to accidentally set an interrupt request flag. To avoid unwanted interrupts, take these precautions when writing your programs: 1. Disable all interrupts with a DI instruction. 2. Modify the IMOD0 or IMOD1 register. 3. Clear all relevant interrupt request flags. 4. Enable the interrupt by setting the appropriate IEx flag. 5. Enable all interrupts with an EI instructions.
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INTERRUPTS
KS57C0502/C0504/P0504 MICROCONTROLLER
KEY INTERRUPT MODE REGISTER (IMODK) The mode register for external interrupts at the KS0-KS2 pins, IMODK, is a 4-bit register at RAM address FB6H. IMODK is addressable only by 4-bit write instructions. RESET clears all IMODK bits to logic zero. FB6H "0" IMODK.2 IMODK.1 IMODK.0
When bits in the IMODK register are set to logic one, INTK uses the falling edge of an incoming signal at corresponding pins as the interrupt request trigger. When a falling edge is detected at any one of the pins KS0- KS2, the IRQK flag is set to logic one and a release signal for power-down mode is generated. Table 7-6. IMODK Register Bit Settings IMODK 0 IMODK.2 0 0 0 0 1 1 1 1 IMODK.1 0 0 1 1 0 0 1 1 IMODK.0 0 1 0 1 0 1 0 1 Effect of IMODK Settings Disable key interrupt Select falling edge at KS0 Select falling edge at KS1 Select falling edge at KS0-KS1 Select falling edge at KS2 Select falling edge at KS0, KS2 Select falling edge at KS1-KS2 Select falling edge at KS0-KS2
KS2 KS1 KS0 FALLING EDGE DETECTION CIRCUIT IMODK IRQK NOTES: 1. To generate a key interrupt on a falling edge at KS0-KS2, all KS0-KS2 pins must be configured to input mode. 2. If anyone of the KS0-KS2 pins used for interrupt stays low, a key interrupt is not generated. Since all KS0-KS2 pins are ANDed, the falling edge detection circuit cannot detects a falling edge.
Figure 7-6. Circuit Diagram for KS0-KS2 Pins
7-10
KS57C0502/C0504/P0504 MICROCONTROLLER
INTERRUPTS
+ PROGRAMMING TIP -- Using INTK as a Key Input Interrupt
When the INTK interrupt used as a key interrupt, the key interrupt pin must be set to input. 1. When KS0-KS2 are selected: BITS SMB LD LD LD LD LD LD EMB 15 A,#3H IMODK,A EA,#00H PMG3,EA EA,#40H PUMOD,EA
; ; ;
(IMODK) #3H, KS0-KS2 falling edge select P6 Input mode Enable P6 pull-up resistors
7-11
INTERRUPTS
KS57C0502/C0504/P0504 MICROCONTROLLER
INTERRUPT FLAGS There are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each interrupt, the interrupt master enable flag, which enables or disables all interrupt processing. Interrupt Master Enable Flag (IME) The interrupt master enable flag, IME, enables or disables all interrupt processing. Therefore, even when an IRQx flag is set and its corresponding IEx flag is enabled, the interrupt service routine is not executed until the IME flag is set to logic one. The IME flag is located in the IPR register (IPR.3), and is mapped to bit address FB2H.3. It can be directly be manipulated by EI and DI instructions, regardless of the current value of the enable memory bank flag (EMB). Interrupt Enable Flags (IEx) IEx flags, when set to logic one, enable specific interrupt requests to be serviced. When the interrupt request flag is set to logic one, an interrupt will not be serviced until its corresponding IEx flag is also enabled. Interrupt enable flags are mapped to the RAM address area FB8H-FBFH, and can be read, written, or tested directly by 1-bit instructions (BITS and BITR). IEx flags can be addressed directly at their specific RAM addresses, despite the current value of the enable memory bank (EMB) flag. Interrupt Request Flags (IRQx) Interrupt request flags, located in the RAM area FB8H-FBFH, are read/write addressable by 1-bit or 4-bit instructions. IRQx flags can be addressed directly at their specific RAM addresses, regardless of the current value of the enable memory bank (EMB) flag. When a specific IRQx lag is set to logic one, the corresponding interrupt request is generated. The flag is then automatically cleared to logic zero by hardware when the interrupt has been serviced. Exceptions are the watch timer interrupt request flag, IRQW, and key interrupt request flag IRQK, which must be cleared by software after the interrupt service routine has executed. IRQx flags are also used to execute interrupt requests from software. In summary, follow these guidelines for using IRQx flags: 1. IRQx is set to request an interrupt when an interrupt meets the set condition for interrupt generation. 2. IRQx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the exception of IRQW and IRQ2). 3. When IRQx is set to "1" by software, an interrupt is generated.
7-12
KS57C0502/C0504/P0504 MICROCONTROLLER
INTERRUPTS
INTERRUPT MASTER ENABLE FLAG (IME) The interrupt master enable flag, IME, inhibits or enables all interrupt processing. Therefore, even when an IRQx flag and its corresponding IEx flag is enabled, an interrupt request will not be serviced until the IME flag is set to logic one. The IME flag is the most significant bit of the 4-bit IPR register at RAM location FB2H. IME 0 1 IPR.2 IPR.1 IPR.0 Effect of Bit Settings Inhibit all interrupts Enable all interrupts
You can manipulate the IME flag using EI and DI instructions, despite the current value of the enable memory bank (EMB) flag. INTERRUPT ENABLE FLAGS (IEx) Interrupt enable flags are used to control the execution of service routines for specific interrupt requests. The enable flag has priority over a request flag -- even if the IRQx flag is enabled, the interrupt request will not be serviced until the corresponding IEx flag is set to logic one. Using 1-bit or 4-bit instructions and direct addressing, you can read, write, or test IEx (and IRQx) flags despite the current enable memory bank (EMB) value. The IEx and IRQx flags are mapped to RAM area FB8H-FBFH. Table 7-7. Interrupt Enable and Interrupt Request Flag Addresses Address FB8H FBAH FBBH FBCH FBDH FBEH FBFH Bit 3 0 0 0 0 0 IE1 0 Bit 2 0 0 0 0 0 IRQ1 0 Bit 1 IEB IEW 0 IET0 IES IE0 IEK Bit 0 IRQB IRQW 0 IRQT0 IRQS IRQ0 IRQK
NOTES: 1. IEx refers generically to all interrupt enable flags. 2. IRQx refers generically to all interrupt request flags. 3. IEx = 0 is interrupt disable mode. 4. IEx = 1 is interrupt enable mode.
7-13
INTERRUPTS
KS57C0502/C0504/P0504 MICROCONTROLLER
INTERRUPT REQUEST FLAGS (IRQx) When an interrupt request flag (IRQx) is set, a software-generated interrupt is enabled for the corresponding interrupt. IRQx flags can be written by 1- or 4-bit RAM control instructions. IRQx flags are then cleared automatically when the interrupt has been serviced. Exceptions to the general rule are the watch timer interrupt request flag, IRQW and key interrupt request flag, IRQK; they must be cleared by software after the interrupt service routine has executed. Table 7-8. Interrupt Request Flag Conditions and Priorities Interrupt Source INTB INT0 INT1 INTS INTT0 INTK * INTW * Internal / External I E E I I E I Pre-condition for IRQx Flag Setting Reference time interval signal from basic timer Rising or falling edge detected at INT0 pin Rising or falling edge detected at INT1 pin Completion signal for serial transmit-and-receive or receive-only operation Signals for TCNT0 and TREF0 registers coincide Falling edge is detected at any one of the KS0- KS2 pins Time interval of 0.5 secs or 3.19 msecs Interrupt Priority 1 2 3 4 5 -- -- IRQx Flag Name IRQB IRQ0 IRQ1 IRQS IRQT0 IRQK IRQW
*
INTK and INTW are quasi-interrupts and INTK is used only for testing incoming signals.
7-14
KS57C0502/C0504/P0504 MICROCONTROLLER
POWER-DOWN
8
POWER-DOWN
OVERVIEW The KS57C0502/C0504 microcontroller has two power-down modes to reduce power consumption: idle and stop. Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP instructions must always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while peripherals and the oscillation source continue to operate normally. When RESET occurs during normal operation or during a power-down mode, a reset operation is initiated and the CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has elapsed, normal CPU operation resumes. In stop mode, system clock oscillation is halted (assuming it is currently operating), and peripheral hardware components are powered-down. The effect of stop mode on specific peripheral hardware components -- CPU, basic timer, serial I/O, timer/ counters 0, and watch timer -- and on external interrupt requests, is detailed in Table 8-1. NOTE Do not use stop mode if you are using an external clock source because Xin input must be restricted internally to VSS to reduce current leakage. Idle or stop modes are terminated either by a RESET, or by an interrupt with the exception of INT0, which are enabled by the corresponding interrupt enable flag, IEx. When power-down mode is terminated by RESET input, a normal reset operation is executed. Assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down mode is released immediately upon entering power-down mode. When an interrupt is used to release power-down mode, the operation differs depending on the value of the interrupt master enable flag (IME): -- If the IME flag = "0", program execution is started immediately after the instruction which issues the request to enter power-down mode. The interrupt request flag remains set to logic one. -- If the IME flag = "1", two instructions are executed after the power-down mode release. Then, the vectored interrupt is initiated. However, when the release signal is caused by INTK or INTW, the operation is identical to the IME = 0 condition. That is, a vector interrupt is not generated.
8-1
POWER-DOWN
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 8-1. Hardware Operation During Power-Down Modes Operation Clock oscillator Basic timer Serial interface Timer/counter 0 Comparator Watch timer External interrupts CPU Power-down mode release signal Stop Mode (STOP) System clock oscillation stops Basic timer stops Operates only if external SCK input is selected as the serial I/O clock Operates only if TCL0 is selected as the counter clock Comparator operation is stopped Watch timer operation is stopped INT1 and INTK are acknowledged; INT0 is not serviced All CPU operations are disabled Idle Mode (IDLE) CPU clock oscillation stops (system clock oscillation continues) Basic timer operates (with IRQB set at each reference interval) Operates if a clock other than the CPU clock is selected as the serial I/O clock Timer/counter 0 operates Comparator operates Watch timer operates INT1 and INTK are acknowledged; INT0 is not serviced All CPU operations are disabled
Interrupt request signals (except INT0) Interrupt request signals (except INT0) are enabled by an interrupt enable flag or are enabled by an interrupt enable flag or by RESET input by RESET input
8-2
KS57C0502/C0504/P0504 MICROCONTROLLER
POWER-DOWN
IDLE MODE TIMING DIAGRAMS
IDLE INSTRUCTION
RESET
OSCILLATION STABILIZATION (31.3 ms / 4.19 MHz)
NORMAL MODE
IDLE MODE
NORMAL MODE
CLOCK SIGNAL
NORMAL OSCILLATION
Figure 8-1. Timing When Idle Mode is Released by RESET
IDLE INSTRUCTION MODE RELEASE SIGNAL NORMAL MODE IDLE MODE INTERRUPT ACKNOWLEDGE (IME = 1)
NORMAL MODE
CLOCK SIGNAL
NORMAL OSCILLATION
Figure 8-2. Timing When Idle Mode is Released by an Interrupt
8-3
POWER-DOWN
KS57C0502/C0504/P0504 MICROCONTROLLER
STOP MODE TIMING DIAGRAMS
STOP INSTRUCTION
RESET
OSCILLATION STABILIZATION (31.3 ms / 4.19 MHz)
NORMAL MODE
STOP MODE OSCILLATION STOPS
IDLE MODE
NORMAL MODE
CLOCK SIGNAL
OSCILLATION RESUMES
Figure 8-3. Timing When Stop Mode is Released by RESET
STOP INSTRUCTION MODE RELEASE SIGNAL NORMAL MODE STOP MODE OSCILLATION STOPS
OSCILLATION STABILIZATION (BMOD SETTING) INT ACK (IME = 1)
IDLE MODE
NORMAL MODE
CLOCK SIGNAL
OSCILLATION RESUMES
Figure 8-4. Timing When Stop Mode is Release by an Interrupt
8-4
KS57C0502/C0504/P0504 MICROCONTROLLER
POWER-DOWN
I/O PORT PIN CONFIGURATION FOR POWER-DOWN The following method describes how to configure I/O port pins to reduce power consumption during powerdown modes (stop, idle): Condition 1: If the microcontroller is not configured to an external device:
1. Connect unused port pins according to the information in Table 8-2. 2. Disable all pull-up resistors for output pins by making the appropriate modifications to the pull-up resistor mode register, PUMOD. Reason: If output goes low when the pull-up resistor is enabled, there may be unexpected surges of current through the pull-up. 3. Disable pull-up resistors for input pins configured to VDD or VSS levels in order to check the current input option. Reason: If the input level of a port pin is set to VSS when a pull-up resistor is enabled, it will draw an unnecessarily large current. Condition 2: If the microcontroller is configured to an external device and the external device's VDD source is turned off in power-down mode.
1. Connect unused port pins according to the information in Table 8-2. 2. Disable the pull-up resistors of output pins by making the appropriate modifications to the pull-up resistor mode register, PUMOD. Reason: If output goes low when the pull-up resistor is enabled, there may be unexpected surges of current through the pull-up. 3. Disable pull-up resistors for input pins configured to VDD or VSS levels in order to check the current input option. Reason: If the input level of a port pin is set to VSS when a pull-up resistor is enabled, it will draw an unnecessarily large current. 4. Disable the pull-up resistors of input pins connected to the external device by making the necessary modifications to the PUMOD register. 5. Configure the output pins that are connected to the external device to low level. Reason: When the external device's VDD source is turned off, and if the microcontroller's output pins are set to high level, VDD - 0.7 V is supplied to the VDD of the external device through its input pin. This causes the device to operate at the level VDD - 0.7 V. In this case, total current consumption would not be reduced. 6. Determine the correct output pin state necessary to block current pass in according with the external transistors (PNP, NPN).
8-5
POWER-DOWN
KS57C0502/C0504/P0504 MICROCONTROLLER
RECOMMENDED CONNECTIONS FOR UNUSED PINS To reduce overall power consumption, please configure unused pins according to the guidelines described in Table 8-2. Table 8-2. Unused Pin Connections for Reduced Power Consumption Pin/Share Pin Names P0.0 / SCK P0.1 / SO P0.2 / SI P1.0 / INT0 - P1.1 / INT1 P2.0 / CIN0 P2.1 / CIN1 P2.2 / CIN2 P2.3 / CIN3 P3.0 / TCLO0 P3.1 / TCLO1 P3.2 / CLO P3.3 / BUZ P4.0-P4.3 P5.0-P5.3 P6.0 / KS0 - P6.3 / BUZ Recommended Connection Input mode: Connect to VDD Output mode: Do not connect Connect to VDD Connect to VDD
Input mode: Connect to VDD Output mode: Do not connect
8-6
KS57C0502/C0504/P0504 MICROCONTROLLER
RESET
9
RESET
OVERVIEW When a RESET signal is input during normal operation or power-down mode, a reset operation is initiated and the CPU enters idle mode. Then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 MHz has elapsed, normal system operation resumes. Regardless of when the RESET occurs -- during normal operating mode or during power-down mode -- the effect on most hardware register values is almost identical. The exceptions are as follows: -- Carry flag -- Data memory values -- General-purpose registers E, A, L, H, X, W, Z, and Y -- Serial I/O buffer register (SBUF) If a RESET occurs during idle or stop mode, the current values in these registers are retained. Otherwise, their values are undefined.
OSCILLATION STABILIZATION (31.3 ms / 4.19 MHz)
RESET
INPUT
NORMAL MODE OR POWER-DOWN MODE RESET OPERATION
IDLE MODE
OPERATING MODE
Figure 9-1. Timing for Oscillation Stabilization After RESET
HARDWARE REGISTER VALUES AFTER RESET Table 9-1 gives you detailed information about hardware register values after a RESET occurs during powerdown mode or during normal operation.
9-1
RESET
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 9-1. Hardware Register Values After RESET Hardware Component or Subcomponent Program counter (PC) If RESET Occurs During Power-Down Mode If RESET Occurs During Normal Operation
Lower three bits of address 0000H Lower three bits of address 0000H are transferred to PC11-8, and the are transferred to PC11-8, and the contents of 0001H to PC7-0. contents of 0001H to PC7-0.
Program Status Word (PSW): Carry flag (C) Skip flag (SC0-SC2) Interrupt status flags (IS0, IS1) Bank enable flags (EMB, ERB) Retained 0 0 Bit 6 of address 0000H in program memory is transferred to the ERB flag, and bit 7 of the address to the EMB flag. Undefined Undefined 0 0 Bit 6 of address 0000H in program memory is transferred to the ERB flag, and bit 7 of the address to the EMB flag. Undefined
Stack pointer (SP) Data Memory (RAM): General registers E, A, L, H, X, W, Z, Y General-purpose registers Bank selection registers (SMB, SRB) BSC register (BSC0-BSC3) Clocks: Power control register (PCON) Clock output mode register (CLMOD) Interrupts: Interrupt request flags (IRQx) Interrupt enable flags (IEx) Interrupt priority flag (IPR) Interrupt master enable flag (IME) INT0 mode register (IMOD0) INT1 mode register (IMOD1) INTK mode register (IMODK)
NOTE:
Values retained Values retained (Note) 0, 0 0
Undefined Undefined 0, 0 0
0 0
0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
The values of the 0F8H-0FDH are not retained when a RESET signal is input
9-2
KS57C0502/C0504/P0504 MICROCONTROLLER
RESET
Table 9-1. Hardware Register Values After RESET (Continued) Hardware Component or Subcomponent I/O Ports: Output buffers Output latches Port mode flags (PM) Pull-up resistor mode reg (PUMOD) Port 2 mode register (PWMOD) Port open-drain enable register (PNE) Watch-dog Timer: WDT mode register (WDMOD) WDT clear flag (WDTCF) Basic Timer: Count register (BCNT) Mode register (BMOD) Timer/Counter 0: Count registers (TCNT0) Reference registers (TREF0) Mode registers (TMOD0) Output enable flags (TOE0) Watch Timer: Watch timer mode register (WMOD) Comparator Comparator mode register (CMOD) Comparison result register Serial I/O Interface: SIO mode register (SMOD) SIO interface buffer (SBUF) 0 Values retained 0 Undefined 0 Undefined 0 Undefined 0 0 0 FFH, FFFFH 0 0 0 FFH, FFFFH 0 0 Undefined 0 Undefined 0 A5H 0 A5H 0 Off 0 0 0 0 0 Off 0 0 0 0 0 If RESET Occurs During Power-Down Mode If RESET Occurs During Normal Operation
9-3
RESET
KS57C0502/C0504/P0504 MICROCONTROLLER
NOTES
9-4
KS57C0502/C0504/P0504 MICROCONTROLLER
I/O PORTS
10
OVERVIEW
I/O PORTS
The KS57C0502/C0504 has two input ports and five I/O ports. Pin addresses for all I/O ports are mapped to locations FF0H-FF6H in bank 15 of the RAM. The contents of I/O port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. There are total of 6 input pins and 18 configurable I/O pin, including 8 high current I/O pins for a maximum number of 24 I/O pins. Port Mode Flags Port mode flags (PM) are used to configure I/O ports 0 and 3 (port mode group 1), port 4 (port mode group 2), and ports 5 and 6 (port mode group 3) to input or output mode by setting or clearing the corresponding I/O buffer. PM flags are stored in three 8-bit registers in RAM area FE8H-FEDH, and are addressable by 8-bit write instructions only. Port 2 Mode Register Port 2 (P2.0-P2.3) can be used as either for analog input or for digital input. P2MOD register settings determines port 2 mode (analog or digital input) for specific port 2 pins. Pull-Up Resistors Pull-up resistors are assignable to input pins of ports 0, 1, 3, 4, 5 and 6. When a configurable I/O port pin serves as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up resistor is enabled by a corresponding bit setting in the pull-up resistor mode register (PUMOD). PUMOD Control Register The pull-up mode register (PUMOD) is an 8-bit register used to assign internal pull-up resistors by software to specific I/O ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting. PUMOD is mapped to RAM address FDCH-FDDH and is addressable by 8-bit write instructions only. RESET clears PUMOD register values to logic zero, automatically disconnecting all software-assignable port pull-up resistors.
10-1
I/O PORTS
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 10-1. I/O Port Overview Port 0 I/O I/O Pins 3 Pin Names P0.0-P0.2 Address FF0H Function Description 3-bit I/O port. 1-bit and 3-bit read/write and test is possible. Individual pins are software configurable as input or output. 3-bit pull-up resistors are assignable by software. 2-bit input port. 1-bit and 2-bit read and test is possible. 2-bit pull-up resistors are software assignable. 4-bit analog or digital input port. 1-bit or 4-bit read and test possible. Same as port 0. 4-bit I/O ports. 1-, 4-, and 8-bit read/write/test is possible. Pins are individually configurable as input or output. Ports 4 and 5 can be paired to support 8-bit data transfer. 4-bit pull-up registers are software assignable to input pins and are automatically disabled for output pins. The N-channel open drain or push-pull output can be selected by software (1-bit unit) 4-bit I/O ports. Pins are individually software configurable as input or output. 1-bit and 4-bit read/write/test is possible. 4-bit pull-up resistors are software assignable.
1
I
2
P1.0-P1.1
FF1H
2 3 4, 5
I I/O I/O
4 3 8
P2.0-P2.3 P3.0-P3.2 P4.0-P4.3 P5.0-P5.3
FF2H FF3H FF4H FF5H
6
I/O
4
P6.0-P6.3
FF6H
Table 10-2. I/O Port Pin Status During Instruction Execution Instruction Type 1-bit test 1-bit input 4-bit input 8-bit input 1-bit output 4-bit output 8-bit output Example BTST LDB LD LD BITR LD LD P0.1 C,P1.3 A,P6 EA,P4 P3.0 P2,A P6,EA Input Mode Status Input or test data at each pin Output Mode Status Input or test data at output latch
Output latch contents undefined Transfer accumulator data to the output latch
Output pin status is modified Transfer accumulator data to the output pin
10-2
KS57C0502/C0504/P0504 MICROCONTROLLER
I/O PORTS
PORT MODE FLAGS (PM FLAGS) Port mode flags (PM) are used to configure I/O ports 0 and 3-6 to input or output mode by setting or clearing the corresponding I/O buffer. PM flags are stored in three 8-bit registers in RAM area FE8H-FEDH, and are addressable by 8-bit write instructions only. For convenient program reference, PM flags are organized into three groups -- PMG1, PMG2, and PMG3, as shown in Table 10-3. Table 10-3. Port Mode Groups and Corresponding I/O Ports Port Mode Group ID PMG1 PMG2 PMG3 Corresponding I/O Ports Ports 0 and 3 Port 4 Ports 5 and 6 Port Mode Group Address FE8H-FE9H FEAH-FEBH FECH-FEDH
When a PM flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. RESET clears all port mode flags to logic zero, automatically configuring the corresponding I/O ports to input mode. Table 10-4. Port Mode Flag Map PM Group ID PMG1 PMG2 PMG3 Address FE8H FE9H FEAH FEBH FECH FEDH
NOTE:
Bit 3 "0" "0" PM4.3 "0" PM5.3 PM6.3
Bit 2 PM0.2 PM3.2 PM4.2 "0" PM5.2 PM6.2
Bit 1 PM0.1 PM3.1 PM4.1 "0" PM5.1 PM6.1
Bit 0 PM0.0 PM3.0 PM4.0 "0" PM5.0 PM6.0
If bit = "0", the corresponding I/O pin is set to input mode. If bit = "1", the pin is set to output mode. All flags are cleared to "0" following RESET.
+ PROGRAMMING TIP -- Configuring I/O Ports as Input or Output
Configure P0.0 and P3.0 as an output port and the other ports as input ports: BITS SMB LD LD LD LD LD LD EMB 15 EA,#11H PMG1,EA EA,#00H PMG2,EA EA,#00H PMG3,EA
; ; ;
P0.0 and P3.0 Output P4 Input P5, P6 Input
10-3
I/O PORTS
KS57C0502/C0504/P0504 MICROCONTROLLER
PORT 2 MODE REGISTER (P2MOD) P2MOD register settings determine if port 2 is used either for analog input or for digital input. P2MOD register is 4-bit write only register. P2MOD is mapped to address FE2H and initialized to zero by a RESET, configuring port 2 as an analog input port. FE2H P2MOD.3 P2MOD.2 P2MOD.1 P2MOD.0
When bit is set to "1", the corresponding pin is configured as a digital input pin. When set to "0", configured as an analog input pin: P2MOD.0 for P2.0, P2MOD.1 for P2.1, P2MOD.2 for P2.2, and P2MOD.3 for P2.3. PULL-UP RESISTOR MODE REGISTER (PUMOD) The pull-up resistor mode register (PUMOD) is an 8-bit register used to assign internal pull-up resistors by software to specific I/O ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting. PUMOD is mapped to RAM address FDCH-FDDH and is addressable by 8-bit write instructions only. RESET clears PUMOD register values to logic zero, automatically disconnecting all software-assignable port pull-up resistors. Table 10-5. Pull-Up Resistor Mode Register (PUMOD) Organization Address FDCH FDDH
NOTE:
Bit 3 PUMOD.3 "0"
Bit 2 "0" PUMOD.6
Bit 1 PUMOD.1 PUMOD.5
Bit 0 PUMOD.0 PUMOD.4
When bit = "1", a pull-up resistor is assigned to the corresponding I/O port: PUMOD.3 for port 3, PUMOD.6 for port 6, and so on.
N-CHANNEL OPEN-DRAIN ENABLE REGISTER (PNE) Address PNE FDAH FDBH Bit 3 PNE4.3 PNE5.3 Bit 2 PNE4.2 PNE5.2 Bit 1 PNE4.1 PNE5.1 Bit 0 PNE4.0 PNE5.0
The N-channel, open-drain mode register, PNE, is used to configure ports 4 and 5 to n-channel, open-drain mode or as push-pull outputs. When a bit in the PNE register is set to "1", the corresponding output pin is configured to n-channel, opendrain; when set to "0", the output pin is configured to push-pull; PNE4.3 for P4.3, PNE4.2 for P4.2, PNE4.1 for P4.1, PNE4.0 for P4.0, PNE5.3 for P5.3, PNE5.2 for P5.2, PNE5.1 for P5.1 and PNE5.0 for P5.0.
+ PROGRAMMING TIP -- Enabling and Disabling I/O Port Pull-Up Resistors
P6 enable pull-up resistors, P0, P1, P3, P4 and P5 disable pull-up resistors. BITS SMB LD LD EMB 15 EA,#40H PUMOD,EA
;
P6 enable
10-4
KS57C0502/C0504/P0504 MICROCONTROLLER
I/O PORTS
PORT 0 CIRCUIT DIAGRAM
SCK
P0.0
LATCH
SMOD.1 P0.1 SO LATCH
P0.2
LATCH
SMOD.7 SMOD.6 SMOD.5
VDD
SCK
SI
PUMOD.0 PM0.2 PUMOD.0 PM0.1 PUMOD.0 PM0.0
P0.0 /SCK P0.1 / SO P0.2 / SI
NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).
Figure 10-1. I/O Port 0 Circuit Diagram
10-5
I/O PORTS
KS57C0502/C0504/P0504 MICROCONTROLLER
PORT 1 CIRCUIT DIAGRAM
VDD PUMOD.1
VDD
INT0
INT1
IMOD0
P1.0 / INT0 P1.1 / INT1
N/R = Noise reduction
N/R Circuit
Figure 10-2. Input Port 1 Circuit Diagram
10-6
KS57C0502/C0504/P0504 MICROCONTROLLER
I/O PORTS
PORT 2 CIRCUIT DIAGRAM
P2.0 / CIN0
DIGITAL INPUT
ANALOG INPUT P2.1 / CIN1 DIGITAL INPUT
ANALOG INPUT P2.2 / CIN2 DIGITAL INPUT
ANALOG INPUT P2.3 / CIN3 DIGITAL INPUT
ANALOG INPUT EXTERNAL REFERENCE
Figure 10-3. Port 2 Circuit Diagram
10-7
I/O PORTS
KS57C0502/C0504/P0504 MICROCONTROLLER
PORT 3 CIRCUIT DIAGRAM
VDD
TC0 CLOCK OUTPUT
PUMOD.3
CLOCK OUTPUT
PM3.2
PUMOD.3 PM3.1 PUMOD.3 PM3.0
P3.0 / TCL0 P3.1 / TCLO0 P3.2 / CLO OUTPUT LATCH 1, 4
M U X 1, 4
TCL0 NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).
Figure 10-4. Port 3 Circuit Diagram
10-8
KS57C0502/C0504/P0504 MICROCONTROLLER
I/O PORTS
PORTS 4 AND 5 CIRCUIT DIAGRAM
VDD
b=4, 5
P-CH
PUMOD.b
8
P-CH
PNE
8
Px.b
OUTPUT LATCH
N-CH
1, 4, 8
PMx.b x=4, 5 b=0, 1, 2, 3
8
VSS M U X
Figure 10-5. Circuit Diagram for Ports 4 and 5
10-9
I/O PORTS
KS57C0502/C0504/P0504 MICROCONTROLLER
PORT 6 CIRCUIT DIAGRAM
VDD
PUMOD.6 PM6.3 PUMOD.6 PM6.2 PUMOD.6 PM6.1 PUMOD.6 PM6.0
P6.0 / KS0 P6.1 / KS1 P6.2 / KS2 P6.3 / BUZ
OUTPUT LATCH
1, 4
M U X 1, 4
NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).
Figure 10-6. Port 6 Circuit Diagram
10-10
KS57C0502/C0504/P0504 MICROCONTROLLER
TIMERS and TIMER/COUNTER
11
OVERVIEW
TIMERS and TIMER/COUNTER
There are three timer and timer/counter function modules: -- 8-bit basic timer (BT) -- 8-bit timer/counter 0 (TC0) -- Watch timer (WT) The 8-bit basic timer (BT) is the microcontroller's main interval timer. It generates a interrupt request at a fixed time interval by making the appropriate modification to the mode register. The basic timer also functions as a 'watchdog' timer and is used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a RESET. The 8-bit timer/counter 0 (TC0) is programmable timer/counter that is used primarily for event counting and for clock frequency modification and output. In addition, TC0 generates a clock signal that can be used by the serial I/O interface. The watch timer (WT) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. Watch timer functions include real-time and watch-time measurement, system clock interval timing, and generation of buzzer output.
11-1
TIMERS and TIMER/COUNTER
KS57C0502/C0504/P0504 MICROCONTROLLER
BASIC TIMER (BT)
OVERVIEW The 8-bit basic timer (BT) has four functional components: -- Clock selector logic -- 4-bit mode register (BMOD) -- 8-bit counter register (BCNT) The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. You can use the basic timer as a "watchdog" timer for monitoring system events or use BT output to stabilize clock oscillation when stop mode is released by an interrupt and following RESET. Use the basic timer mode register, BMOD, to turn the BT on and off, to select input clock frequency, and to control interrupt or stabilization intervals. Interval Timer Function The measurement of elapsed time intervals is the basic timer's primary function. The standard interval is 256 BT clock pulses. To restart the basic timer, set bit 3 of the mode register BMOD to logic one. The input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to BMOD.2-BMOD.0. The 8-bit counter register, BCNT, is incremented each time a clock signal is detected that corresponds to the frequency selected by BMOD. BCNT continues incrementing as it counts BT clocks until an overflow occurs. An overflow causes the BT interrupt request flag (IRQB) to be set to logic one to signal that the designated time interval has elapsed. An interrupt request is then generated, BCNT is cleared to logic zero, and counting continues from 00H. Watchdog Timer Function The basic timer can also be used as a "watch-dog" timer to detects inadvertent program loop, that is, system or program operation error. For this purpose, instruction that clear the watch-dog timer(BITS WDTCF) should be executed at proper points in a program within a given period. If an instruction that clears the watch-dog timer is not executed within the period and the watch-dog timer overflows, reset signal is generated and system is restarted with reset status. An operation of watch-dog timer is as follows: Write some value(except #5AH) to Watch-Dog Timer Mode register, WDMOD. If WDCNT overflows, system reset is generated. Oscillation Stabilization Interval Control Bits 2-0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when power-down mode is released by an interrupt. When a RESET signal is generated the standard stabilization interval , for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.
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KS57C0502/C0504/P0504 MICROCONTROLLER
TIMERS and TIMER/COUNTER
Table 11-1. Basic Timer Register Overview Register Name BMOD Type Control Description Controls the clock frequency (mode) of the basic timer; also, the oscillation stabilization interval after power-down mode release or RESET Size 4-bit RAM Address F85H Addressing Mode 4-bit writeonly; BMOD.3: also 1-bit writeable 8-bit read-only 8-bit writeonly 1-bit writeonly Reset Value "0"
BCNT WDMOD WDTCF
Counter Counts clock pulses matching the BMOD frequency setting Control Control Controls watch-dog timer operation. Clear the watch-dog timer's counter.
8-bit 8-bit 1-bit
F86H - F87H F98HAF99H F9AH.3
U* A5H "0"
*
'U' means the value is undetermined after a RESET.
"CLEAR" SIGNAL CLEAR BCNT CLEAR IRQB INTERRUPT REQUEST 1-BIT R/W
BITS INSTRUCTION 4
BMOD.3 BMOD.2 BMOD.1 BMOD.0 8
CLOCK INPUT
CLOCK SELECTOR
BCNT
OVERFLOW
IRQB
CPU CLOCK START SIGNAL (POWER-DOWN RELEASE)
1 pulse period=BT input clock 28 (1/2 duty)
3-BIT COUNTER OVERFLOW
WDTCNT
RESET GENERATION
RESET
WDMOD 8
WDTCF WAIT* RESET STOP
CLEAR
DELAY *WAIT means -Stabilization time after RESET - Stabilization time after STOP mode release
BITS INSTRUCTION
Figure 11-1. Basic Timer Circuit Diagram
11-3
TIMERS and TIMER/COUNTER
KS57C0502/C0504/P0504 MICROCONTROLLER
BASIC TIMER MODE REGISTER (BMOD) The basic timer mode register, BMOD, is a 4-bit write-only register located at RAM address F85H. Bit 3, the basic timer start control bit, is also 1-bit addressable. All BMOD values are set to logic zero following RESET and interrupt request signal generation is set to the longest interval. (BT counter operation cannot be stopped.) BMOD settings have the following effects: -- Restart the basic timer, -- Control the frequency of clock signal input to the basic timer, and -- Determine time interval required for clock oscillation to stabilize following the release of stop modes by an interrupt. By loading different values into the BMOD register, you can dynamically modify the basic timer clock frequency during program execution. Four BT frequencies, ranging from fx/212 (1.02 kHz) to fx/25 (131 kHz), are selectable. Since BMOD's reset value is logic zero, the default clock frequency setting is fx/212. (kHz frequencies assume a system clock (fx) frequency of 4.19 MHz.) The most significant bit of the BMOD register, BMOD.3, is used to start the basic timer again. When BMOD.3 is set to logic one (enabled) by a 1-bit write instruction, the contents of the BT counter register (BCNT) and the BT interrupt request flag (IRQB) are both cleared to logic zero, and timer operation is restarted. The combination of bit settings in the remaining three registers -- BMOD.2, BMOD.1, and BMOD.0 -- determine the clock input frequency and oscillation stabilization interval.
Table 11-2. Basic Timer Mode Register (BMOD) Organization BMOD.3 1 Basic Timer Enable/Disable Control Bit Start basic timer; clear IRQB, BCNT, and BMOD.3 to "0"
BMOD.2 0 0 1 1
BMOD.1 0 1 0 1
BMOD.0 0 1 1 1
Basic Timer Input Clock fx/212 (1.02 kHz) fx/29 (8.18 kHz) fx/27 (32.7 kHz) fx/25 (131 kHz)
Oscillation Stabilization 220/fx (250 ms) 217/fx (31.3 ms) 215/fx (7.82 ms) 213/fx (1.95 ms)
NOTES: 1. Clock frequencies and stabilization intervals assume a system oscillator clock frequency (fx) of 4.19 MHz. 2. fx = system clock frequency. 3. Oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released. 4. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.
11-4
KS57C0502/C0504/P0504 MICROCONTROLLER
TIMERS and TIMER/COUNTER
BASIC TIMER COUNTER (BCNT) BCNT is an 8-bit counter register for the basic timer. It is mapped to RAM addresses F86H-F87H and can be addressed by 8-bit read instructions. RESET leaves the BCNT register value undetermined. BCNT is automatically cleared to logic zero whenever the BMOD register control bit (BMOD.3) is set to "1" to restart the basic timer. It is incremented each time a clock pulse of the frequency determined by the current BMOD bit settings is detected. When BCNT has incremented to hexadecimal 'FFH' (256 clock pulses), it is cleared to '00H' and an overflow is generated. The overflow causes the interrupt request flag, IRQB, to be set to logic one. When the interrupt request is generated, BCNT immediately resumes counting incoming clock signals. NOTE Always execute a BCNT read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. If, after two consecutive reads, the BCNT values match, you can select the latter value as valid data. Until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met. BASIC TIMER OPERATION SEQUENCE The basic timer's sequence of operations may be summarized as follows: 1. Set bit BMOD.3 to logic one to restart basic timer operation 2. BCNT is incremented by one after each clock pulse corresponding to BMOD selection 3. BCNT overflows if BCNT 255 (FFH) 4. When an overflow occurs, the IRQB flag is set to logic one by hardware 5. The interrupt request is generated 6. BCNT is automatically cleared to logic zero (BCNT = 00H) 7. BCNT resumes counting BT clock pulse
11-5
TIMERS and TIMER/COUNTER
KS57C0502/C0504/P0504 MICROCONTROLLER
+ PROGRAMMING TIP -- Using the Basic Timer
1. To read the basic timer count register (BCNT): BITS SMB LD LD LD CPSE JR EMB 15 EA,BCNT YZ,EA EA,BCNT EA,YZ BCNTR
BCNTR
2. When stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms: BITS SMB LD LD STOP NOP NOP NOP EMB 15 A,#0BH BMOD,A
; ;
Wait time is 31.3 ms Set stop power-down mode
CPU OPERATION
NORMAL OPERATING MODE
STOP MODE
IDLE MODE (31.3 ms)
NORMAL OPERATING MODE
STOP INSTRUCTION
STOP MODE IS RELEASED BY INTERRUPT
3. To set the basic timer interrupt interval time to 1.95 ms (at 4.19 MHz): BITS SMB LD LD EI BITS EMB 15 A,#0FH BMOD,A IEB ; Basic timer interrupt enable flag is set to "1"
4. Clear BCNT and the IRQB flag and restart the basic timer: BITS SMB BITS EMB 15 BMOD.3
11-6
KS57C0502/C0504/P0504 MICROCONTROLLER
TIMERS and TIMER/COUNTER
WATCH-DOG TIMER MODE REGISTER (WDMOD) The watch-dog timer mode register, WDMOD, is a 8-bit write-only register located at RAM address F98H F99H. WDMOD register controls to enable or disable the watch-dog timer function. WDMOD values are set to logic "A5H" following RESET and this value enable the watch-dog timer, and watch-dog time period is set to the longest r's interval becauseBT overflow signal is generated with the longest interval. (BT counter operation cannot be stopped.) WDMOD - Watch-Dog Timer Mode Control Register Bit Identifier
RESET Value
F99H,F98H 0 .4 0 W 3 .3 0 W 2 .2 1 W 1 .1 0 W 0 .0 1 W
3 .7 1 W WDMOD 5AH Any other Value
2 .6 0 W
1 .5 1 W
Read/Write
Watch-Dog Timer Enable/Disable Control Disable Watch-dog timer function Enable Watch-dog timer function
WATCH-DOG TIMER COUNTER (WDCNT) WDCNT is an 3-bit counter. WDCNT is automatically cleared to logic zero whenever the WDTCF register control bit (WDTCF) is set to "1" to restart the WDCNT. Reset, stop, and wait signal clear the WDCNT to logic zero also. WDCNT is incremented each time a clock pulse of the overflow frequency determined by the current BMOD bit settings. When WDCNT has incremented to hexadecimal '07H' (8 BT overflow pulses), it is cleared to '00H' and an overflow is generated. The overflow causes the system reset. When the interrupt request is generated, BCNT immediately resumes counting incoming clock signals. WATCH-DOG TIMER'S COUNTER CLEAR FLAG(WDTCF) WDTCF(F9AH.3) setting clear the WDT's counter to zero and restart the WDT's counter. Table 11-3. Watch-Dog Timer Interval Time BMOD x000b x011b x101b x111b BT Input Clock 212 /fx 29/fx 27/fx 25/fx WDCNT input clock 212 /fx x 28 29/fx x 28 27/fx x 28 25/fx x 28 WDT interval time 212 /fx x 28 x 23 29/fx x 28 x 23 27/fx x 28 x 23 25/fx x 28 x 23 Main clock 2 sec 250 msec 62.5 msec 15.6 msec
NOTES: 1. Clock frequencies assume a system oscillator clock frequency (fx) of : Main clock 4.19MHz 2. fx = system clock frequency.
11-7
TIMERS and TIMER/COUNTER
KS57C0502/C0504/P0504 MICROCONTROLLER
8-BIT TIMER/COUNTER 0 (TC0)
Timer/counter 0 (TC0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has elapsed, TC0 generates an interrupt request. By counting signal transitions and comparing the current counter value with the reference register value, TC0 can be used to measure specific time intervals. TC0 has a reloadable counter that consists of two parts: an 8-bit reference register (TREF0) into which you write the counter reference value, and an 8-bit counter register (TCNT0) whose value is automatically incremented by counter logic. An 8-bit mode register, TMOD0, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. You can modify the basic frequency dynamically by loading new values into TMOD0 during program execution. TC0 FUNCTION SUMMARY 8-bit programmable timer Generates interrupts at specific time intervals based on the selected clock frequency. Counts various system "events" based on edge detection of external clock signals at the TC0 input pin, TCL0. To start the event counting operation, TMOD0.2 is set to "1" and TMOD0.6 is cleared to "0". Outputs selectable clock frequencies to the TC0 output pin, TCLO0. Divides the frequency of an incoming external clock signal according to a modifiable reference value (TREF0), and outputs the modified frequency to the TCLO0 pin. Outputs a modifiable clock signal for use as the SCK clock source.
External event counter
Arbitrary frequency output External signal divider
Serial I/O clock source
11-8
KS57C0502/C0504/P0504 MICROCONTROLLER
TIMERS and TIMER/COUNTER
TC0 COMPONENT SUMMARY Mode register (TMOD0) Reference register (TREF0) Counter register (TCNT0) Clock selector circuit 8-bit comparator Activates the timer/counter and selects the internal clock frequency or the external clock source at the TCL0 pin. Stores the reference value for the desired number of clock pulses between interrupt requests. Counts internal or external clock pulses based on the bit settings in TMOD0 and TREF0. Together with the mode register (TMOD0), lets you select one of four internal clock frequencies, or external clock frequency. Determines when to generate an interrupt by comparing the current value of the counter register (TCNT0) with the reference value previously programmed into the reference register (TREF0). Where a TC0 interrupt request or clock pulse is stored pending output to the serial I/O circuit or to the TC0 output pin, TCLO0. When the contents of the TCNT0 and TREF0 registers coincide, the timer/counter interrupt request flag (IRQT0) is set to "1", the status of TOL0 is inverted, and an interrupt is generated. Output enable flag (TOE0) Interrupt request flag (IRQT0) You must set this flag to logic one before the contents of the TOL0 latch can be output to TCLO0. This flag is cleared when TC0 operation starts and the TC0 interrupt service routine is executed and is enabled whenever the counter value and reference value coincide. Must be set to logic one before the interrupt requests generated by timer/counter can be processed.
Output latch (TOL0)
Interrupt enable flag (IET0)
Table 11-4. TC0 Register Overview Register Name TMOD0 Type Control Description Controls TC0 restart (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6-4) Counts clock pulses matching the TMOD0 frequency setting Stores reference value for the timer/counter 0 interval setting Controls timer/counter 0 output to the TCLO0 pin Size 8-bit RAM Address F90H-F91H Addressing Mode 8-bit writeonly; (TMOD0.3 is also 1-bit write-only) 8-bit read-only 8-bit write-only 1-bit write-only Reset Value "0"
TCNT0 TREF0 TOE0
Counter Reference Flag
8-bit 8-bit 1-bit
F94H-F95H F96H-F97H F92H.2
"0" FFH "0"
11-9
TIMERS and TIMER/COUNTER
KS57C0502/C0504/P0504 MICROCONTROLLER
P3.0 TCL0 TMOD0.7 TMOD0.6 8 TMOD0.5 TMOD0.4 TMOD0.3 TMOD0.2 TMOD0.1 TMOD0.0 CLEAR
CLOCKS (fx/210, fx/2 6, fx/2 4 fx) ,
8 CLOCK SELECTOR TCNT0 8-BIT COMPARATOR CLEAR
8 TREF0
SET CLEAR
INVERTED TOL0 SERIAL I/O
IRQT0
TCLO0 PM3.1 P3.1 LATCH TOE0
Figure 11-2. TC0 Circuit Diagram
TC0 ENABLE/DISABLE PROCEDURE Enable Timer/Counter 0 -- -- -- Set TMOD.2 to logic one (RAM address F90H.2) Set the TC0 interrupt enable flag IET0 to logic one (RAM address FBCH.1) Set TMOD0.3 to logic one (RAM address F90H.3)
TCNT0, IRQT0, and TOL0 are cleared to logic zero, and timer/counter operation starts. Disable Timer/Counter -- Set TMOD0.2 to logic zero (RAM address F90H.2)
Clock signal input to the counter register TCNT0 is halted. The current TCNT0 value is retained and can be read if necessary.
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KS57C0502/C0504/P0504 MICROCONTROLLER
TIMERS and TIMER/COUNTER
TC0 PROGRAMMABLE TIMER/COUNTER FUNCTION Timer/counter 0 can be programmed to generate interrupt requests at various intervals, based on the system clock frequency you select. The 8-bit TC0 mode register, TMOD0, is used to activate the timer/counter and to select the clock frequency. The reference register, TREF0, stores your value for the number of clock pulses to be generated between interrupt requests. The counter register, TCNT0, counts the incoming clock pulses, which are compared to the TREF0 value as TCNT0 is incremented. When there is a match (TREF0 = TCNT0), an interrupt request is generated. To program timer/counter to generate interrupt requests at specific intervals, you choose one of four internal clock frequencies (divisions of the system clock, fx) and load your own counter reference value into the TREF0 register. TCNT0 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by TMOD0.4-TMOD0.6 settings. To generate an interrupt request, the TC0 interrupt request flag (IRQT0) is set to logic one, the status of TOL0 is inverted, and the interrupt is generated. The content of TCNT0 is then cleared to 00H, and TC0 continues counting. The interrupt request mechanism for the programmable timer/counter consists of the TC0 interrupt enable flag IET0 and the TC0 interrupt request flag IRQT0. TC0 OPERATION SEQUENCE The general sequence of operations when using TC0 as a programmable timer/counter can be summarized as follows: 1. Set TMOD0.2 to "1" to enable TC0 2. Set TMOD0.6 to "1" to enable the system clock (fx) input 3. Set TMOD0.5 and TMOD0.4 bits to desired internal frequency (fx/2n) 4. Load a value to TREF0 to specify the interval between interrupt requests 5. Set the TC0 interrupt enable flag (IET0) to "1" 6. Set TMOD0.3 bit to "1" to clear TCNT0, IRQT0, and TOL0, and start counting 7. TCNT0 increments with each internal clock pulse 8. When the comparator shows TCNT0 = TREF0, the IRQT0 flag is set to "1" 9. Output latch (TOL0) logic toggles high or low 10. Interrupt request is generated 11. TCNT0 is cleared to 00H and counting resumes 12. Programmable timer/counter operation continues until TMOD0.2 is cleared to "0".
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TIMERS and TIMER/COUNTER
KS57C0502/C0504/P0504 MICROCONTROLLER
TC0 EVENT COUNTER FUNCTION Timer/counter 0 can be used to monitor or detect system 'events' by using the external clock input at the TCL0 pin (I/O port 3.0) as the counter source. The TC0 mode register is used to specify rising or falling edge detection for incoming clock signals. The counter register TCNT0 is incremented each time the selected state transition of the external clock signal occurs. To activate the TC0 event counter function, -- Set TMOD0.2 to "1" to enable TC0 -- Clear TMOD0.6 to "0" to select the external clock source at the TCL0 pin -- Select TCL0 edge detection for rising or falling signal edges by loading the appropriate values to TMOD0.5 and TMOD0.4. -- P3.0 must be set to input mode.
Table 11-5. TMOD0 Settings for TCL0 Edge Detection TMOD0.5 0 0 TMOD0.4 0 1 TCL0 Edge Detection Rising edges Falling edges
With the exception of the different TMOD0.4-TMOD0.6 settings, the operation sequence for TC's event counter function is identical to its programmable counter/timer function.
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KS57C0502/C0504/P0504 MICROCONTROLLER
TIMERS and TIMER/COUNTER
TC0 CLOCK FREQUENCY OUTPUT Using timer/counter, you can output a modifiable clock frequency to the TC0 clock output pin, TCLO0. To select the clock frequency, you load appropriate values to the TC0 mode register, TMOD0. The clock interval is determined by loading the desired reference value into the reference register TREF0. Then, to enable the output to the TCLO0 pin at I/O port 3.1, the following conditions must be met: -- TC0 output enable flag TOE0 must be set to "1" -- I/O mode flag for P3.1 (PM3.1) must be set to output mode ("1") -- Output latch value for P3.1 must be set to "0" In summary, the operational sequence required to output a TC0-generated clock signal to the TCLO0 pin is as follows: 1. Load your reference value to TREF0 2. Set the clock frequency in TMOD0 3. Initiate TC0 clock output to TCLO0 (TMOD0.2 = "1") 4. Set port 3 mode flag (PM3.1) to "1" 5. Set P3.1 output latch to "0" 6. Set TOE0 flag to "1" Each time TCNT0 overflows and an interrupt request is generated, the state of the output latch TOL0 is inverted and the TC0-generated clock signal is output to the TCLO0 pin.
+ PROGRAMMING TIPS -- TC0 Signal Output to the TCLO0 Pin
Output a 30 ms pulse width signal to the TCLO0 pin: BITS SMB LD LD LD LD LD LD BITR BITS EMB 15 EA,#79H TREF0,EA EA,#4CH TMOD0,EA EA,#20H PMG1,EA P3.1 TOE0
; ;
P3.1 Output mode P3.1 clear
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TIMERS and TIMER/COUNTER
KS57C0502/C0504/P0504 MICROCONTROLLER
TC0 SERIAL I/O CLOCK GENERATION Timer/counter 0 can supply a clock signal to the clock selector circuit of the serial I/O interface for data shifter and clock counter operations. (These internal SIO operations are controlled in turn by the SIO mode register, SMOD). This clock generation function enables you to adjust data transmission rates across the serial interface. Use TMOD0 and TREF0 register settings to select the frequency and interval of the TC0 clock signals to be used as SCK input to the serial interface. The generated clock signal is then sent directly to the serial I/O clock selector circuit -- not through the port 3.1 latch and TCLO0 pin. TC0 EXTERNAL INPUT SIGNAL DIVIDER By selecting an external clock source and loading a reference value into the TC0 reference register, TREF0, you can divide the incoming clock signal by the TREF0 value and then output this modified clock frequency to the TCLO0 pin. The sequence of operations used to divide external clock input may be summarized as follows: 1. Load a signal divider value to the TREF0 buffer register 2. Clear TMOD0.6 to "0" to enable external clock input at the TCL0 pin 3. Set TMOD0.5 and TMOD0.4 to desired TCL0 signal edge detection 4. Set port 3.1 mode flag (PM3.1) to output ("1") 5. Set P3.1 output latch to "0" 6. Set TOE0 flag to "1" to enable output of the divided frequency Divided clock signals are then output to the TCLO0 pin.
+ PROGRAMMING TIP -- External TCL0 Clock Output to the TCLO0 Pin
Output external TCL0 clock pulse to the TCLO0 pin (divide by four):
EXTERNAL (TCL0) CLOCK PULSE
TCLO0 OUTPUT PULSE
BITS SMB LD LD LD LD LD LD BITR BITS
EMB 15 EA,#01H TREF0,EA EA,#0CH TMOD0,EA EA,#20H PMG1,EA P3.1 TOE0
; ;
P3.1 Output mode P3.1 clear
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KS57C0502/C0504/P0504 MICROCONTROLLER
TIMERS and TIMER/COUNTER
TC0 MODE REGISTER (TMOD0) TMOD0 is the 8-bit mode control register for timer/counter. It is located at RAM addresses F90H-F91H and is addressable by 8-bit write instructions. One bit, TMOD0.3, is also 1-bit writeable. RESET clears all TMOD0 bits to logic zero and disables TC0 operations. F90H F91H TMOD0.3 "0" TMOD0.2 TMOD0.6 "0" TMOD0.5 "0" TMOD0.4
TMOD0.2 is the enable/disable bit for timer/counter. When TMOD0.3 is set to "1", the contents of TCNT0, IRQT0, and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal TC0 operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register, TCNT0, are retained until TC0 is re-enabled. Use TMOD0.6, TMOD0.5, and TMOD0.4 bit settings together to select the TC0 clock source. This selection involves two variables: -- Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal input at the TCL0 pin, and -- Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in internal TC0 operation.
Table 11-6. TC0 Mode Register (TMOD0) Organization Bit Name TMOD0.7 TMOD0.6 TMOD0.5 TMOD0.4 TMOD0.3 1 Clear TCNT0, IRQT0, and TOL0 and resume counting immediately (This bit is automatically cleared to logic zero immediately after counting resumes.) Disable timer/counter; retain TCNT0 contents Enable timer/counter Value always logic zero LSB value always logic zero F90H 0,1 Specify input clock edge and internal frequency Setting 0 Resulting TC0 Function MSB value always logic zero F91H Address
TMOD0.2 TMOD0.1 TMOD0.0
0 1 0 0
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TIMERS and TIMER/COUNTER
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 11-7. TMOD0.6, TMO0.5, and TMOD0.4 Bit Settings TMOD0.6 0 0 1 1 1 1 TMOD0.5 0 0 0 0 1 1 TMOD0.4 0 1 0 1 0 1 Resulting Counter Source and Clock Frequency External clock input (TCL0) on rising edges External clock input (TCL0) on falling edges fx/210 = 4.09 kHz fx /26 = 65.5 kHz fx/24 = 262 kHz fx = 4.19 MHz
NOTE: 'fx' = system clock
+ PROGRAMMING TIP -- Restarting TC0 Counting Operation
1. Set TC0 timer interval to 4.09 kHz: BITS SMB LD LD EI BITS EMB 15 EA,#4CH TMOD0,EA IET0
2. Clear TCNT0, IRQT0, and TOL0 and restart TC0 counting operation: BITS SMB BITS EMB 15 TMOD0.3
11-16
KS57C0502/C0504/P0504 MICROCONTROLLER
TIMERS and TIMER/COUNTER
TC0 COUNTER REGISTER (TCNT0) The 8-bit counter register for timer/counter, TCNT0, is mapped to RAM addresses F94H-F95H. It is read-only and can be addressed by 8-bit RAM control instructions. RESET sets all TCNT0 register values to logic zero (00H). Whenever TMOD0.3 are enabled, TCNT0 is cleared to logic zero and counting begins. The TCNT0 register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the TMOD0 register (specifically, TMOD0.6, TMOD0.5, and TMOD0.4). Each time TCNT0 is incremented, the new value is compared to the reference value stored in the TC0 reference register, TREF0. When TCNT0 = TREF0, an overflow occurs in the TCNT0 register, the interrupt request flag, IRQT0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed.
COUNT CLOCK TREF0 REFERENCE VALUE = n
TCNT0
0
1
2
...
n-1
n n
0
1
2
. . . n-1
n
0
1
2
...
TOL0
INTERVAL TIME
COUNTING STARTS
IRQT0 SET
IRQT0 SET
Figure 11-3. TC0 Timing Diagram
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TIMERS and TIMER/COUNTER
KS57C0502/C0504/P0504 MICROCONTROLLER
TC0 REFERENCE REGISTER (TREF0) The TC0 reference register TREF0 is an 8-bit write-only register that is mapped to RAM locations F96H and F97H. It is addressable by 8-bit RAM control instructions. RESET initializes the TREF0 value to 'FFH'. TREF0 is used to store a reference value to be compared to the incrementing TCNT0 register in order to identify an elapsed time interval. Reference values will differ depending upon the specific function that TC0 is being used to perform -- as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. During timer/counter operation, the value loaded into the reference register compared to the TCNT0 value. When TCNT0 = TREF0, the TC0 output latch (TOL0) is inverted and an interrupt request is generated to signal the interval or event. The TREF0 value, together with the TMOD0 clock frequency selection, determines the specific TC0 timer interval. Use the following formula to calculate the correct value to load to the TREF0 reference register: 1 TC0 timer interval = (TREF0 value + 1) x TMOD0 frequency setting ( assuming a TREF0 value 0 )
TC0 OUTPUT ENABLE FLAG (TOE0) The 1-bit timer/counter 0 output enable flag TOE0 controls output from timer/counter 0 to the TCLO0 pin. TOE0 is mapped to RAM location F92H.2 and is addressable by 1-bit read and write instructions. Bit 3 F92H 0 Bit 2 TOE0 Bit 1 0 Bit 0 0
When you set the TOE0 flag to "1", the contents of TOL0 can be output to the TCLO0 pin. Whenever a RESET occurs, TOE0 is automatically set to logic zero, disabling all TC0 output. Even when the TOE0 flag is disabled, timer/counter can continue to output an internally-generated clock frequency, via TOL0, to the serial I/O clock selector circuit. TC0 OUTPUT LATCH (TOL0) TOL0 is the output latch for timer/counter. When the 8-bit comparator detects a correspondence between the value of the counter register TCNT0 and the reference value stored in the TREF0 buffer, the TOL0 value is inverted -- the latch toggles high-to-low or low-to-high. Whenever the state of TOL0 is switched, the TC0 signal is output. TC0 output may be directed to the TCLO0 pin at P3.1, or it can be output directly to the serial I/O clock selector circuit as the SCK signal. Assuming TC0 is enabled, when bit 3 of the TMOD0 register is set to "1", the TOL0 latch is cleared to logic zero, along with the counter register TCNT0 and the interrupt request flag, IRQT0, and counting resumes immediately. When TC0 is disabled (TMOD0.2 = "0"), the contents of the TOL0 latch are retained and can be read, if necessary.
11-18
KS57C0502/C0504/P0504 MICROCONTROLLER
TIMERS and TIMER/COUNTER
+ PROGRAMMING TIP -- Setting a TC0 Timer Interval
To set a 30 ms timer interval for TC0, given fx = 4.19 MHz, follow these steps. 1. Select the timer/counter mode register with a maximum setup time of 62.5 ms (assume the TC0 counter clock = fx/210, and TREF0 is set to FFH): 2. Calculate the TREF0 value: 30 ms = TREF0 value + 1 4.09 kHz 30 ms 244 s = 122.9 = 7AH
TREF0 + 1 =
TREF0 value = 7AH - 1 = 79H 3. Load the value 79H to the TREF0 register: BITS SMB LD LD LD LD EMB 15 EA,#79H TREF0,EA EA,#4CH TMOD0,EA
11-19
TIMERS and TIMER/COUNTER
KS57C0502/C0504/P0504 MICROCONTROLLER
WATCH TIMER
OVERVIEW The watch timer is a multi-purpose timer consisting of three basic components: -- 8-bit watch timer mode register (WMOD) -- Clock selector -- Frequency divider circuit Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. It is also used as a clock source for generating buzzer output. Real-Time and Watch-Time Measurement To start watch timer operation, set bit 2 of the watch timer mode register, WMOD.2, to logic one. The watch timer starts, the interrupt request flag IRQW is automatically set to logic one, and interrupt requests commence in 0.5-second intervals. Since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the IRQW flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed. Using a System Clock Source The watch timer can generate interrupts based on the system clock frequency. The system clock (fx) is used as the signal source, according to the following formula: System clock (fx) 128
Watch timer clock (fw) =
= 32.768 kHz
(assuming fx = 4.19 MHz)
Buzzer Output Frequency Generator The watch timer can generate a steady 2 kHz, 4 kHz, 8 kHz, or 16 kHz signal to the BUZ pin. To select the BUZ frequency you want, load the appropriate value to the WMOD register. This output can then be used to actuate an external buzzer sound. To generate a BUZ signal, three conditions must be met: -- The WMOD.7 register bit at F89H.3 is set to "1" -- The output latch for I/O port 6.3 is cleared to "0" -- The port 6.3 output mode flag (PM6.3) set to 'output' mode Timing Tests in High-Speed Mode By setting WMOD.1 (F88H.1) to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. At its normal speed (WMOD.1 = '0'), the watch timer generates an interrupt request every 0.5 seconds. High-speed mode is useful for timing events for program debugging sequences.
11-20
KS57C0502/C0504/P0504 MICROCONTROLLER
TIMERS and TIMER/COUNTER
WATCH TIMER CIRCUIT
P6.3 LATCH WMOD.7 0 WMOD.5 8 WMOD.4 0 WMOD.2 WMOD.1
fw/2 (16 kHz)
PM6.3
BUZ
MUX
fw/16 (2 KHz) fw/8 (4 kHz) fw/4 (8 kHz)
fx = SYSTEM CLOCK fw = WATCH TIMER FREQUENCY
ENABLE /DISABLE
SELECTOR CIRCUIT
IRQW
0 fw/2
7 14
FREQUENCY fw CLOCK DIVIDING SELECTOR 32.768 kHz CIRCUIT
fw/2
(2 Hz)
GND fx/128
Figure 11-4. Watch Timer Circuit Diagram
11-21
TIMERS and TIMER/COUNTER
KS57C0502/C0504/P0504 MICROCONTROLLER
WATCH TIMER MODE REGISTER (WMOD) The watch timer mode register WMOD is used to select specific watch timer operations. It is mapped to RAM locations F88H-F89H and is 8-bit write-only addressable. RESET sets all WMOD bits to logic zero. F88H F89H "0" WMOD.7 WMOD.2 "0" WMOD.1 WMOD.5 "0" WMOD.4
In brief, WMOD settings control the following watch timer functions: -- Watch timer speed control -- Enable/disable watch timer -- Buzzer frequency selection (WMOD.1) (WMOD.2) (WMOD.4) (WMOD.5) -- Enable/disable buzzer output (WMOD.7)
Table 11-8. Watch Timer Mode Register (WMOD) Organization Bit Name WMOD.7 Values 0 1 WMOD.6 WMOD.5 - .4 0 0 1 1 WMOD.3 WMOD.2 WMOD.1 WMOD.0 "0" 0 1 0 1 0 "0" 0 1 0 1 Function Disable buzzer (BUZ) signal output Enable buzzer (BUZ) signal output Always logic zero 2 kHz buzzer (BUZ) signal output 4 kHz buzzer (BUZ) signal output 8 kHz buzzer (BUZ) signal output 16 kHz buzzer (BUZ) signal output Always logic zero Disable watch timer; clear frequency dividing circuits Enable watch timer Normal mode; sets IRQW to 0.5 seconds High-speed mode; sets IRQW to 3.91 ms Always logic zero F88H F89H Address
NOTE: System clock frequency (fx) is assumed to be 4.19 MHz.
11-22
KS57C0502/C0504/P0504 MICROCONTROLLER
TIMERS and TIMER/COUNTER
+ PROGRAMMING TIP -- Using the Watch Timer
1. Select a 0.5 second interrupt, and 2 kHz buzzer enable: BITS SMB LD LD BITR LD LD BITS EMB 15 EA,#80H PMG3,EA P6.3 EA,#84H WMOD,EA IEW
; ;
P6.3 Output mode Clear P6.3 output latch
2. Sample real-time clock processing method: CLOCK BTSTZ RET * * * IRQW ; ; ; ; 0.5 second check No, return Yes, 0.5 second interrupt generation Increment HOUR, MINUTE, SECOND
11-23
TIMERS and TIMER/COUNTER
KS57C0502/C0504/P0504 MICROCONTROLLER
NOTES
11-24
KS57C0502/C0504/P0504 MICROCONTROLLER
COMPARATOR
12
OVERVIEW
COMPARATOR
Port 2 can be used as a analog input port for a comparator. The reference voltage for the 4-channel comparator can be supplied either internally or externally at P2.3. When internal reference voltage is used, four channels (P2.0-P2.3) are used for analog inputs and the internal reference voltage is varies at 16 levels. If an external reference voltage is input at P2.3, the other three pins (P2.0-P2.2) in port 2 are used for analog input. Unused port 2 pins must be connected to VDD. When a conversion is completed, the result is saved in the comparison result register CMPREG. The initial values of the CMPREG are undefined and the comparator operation is disabled by a RESET. The comparator has following components: -- Comparator -- Internal reference voltage generator (4-bit resolution) -- External reference voltage source at P2.3 -- Comparator mode register (CMOD) -- Comparison result register (CMPREG)
12-1
COMPARATOR
KS57C0502/C0504/P0504 MICROCONTROLLER
P2.0 / CIN0 M P2.1 / CIN1 U P2.2 / CIN2 X P2.3 / CIN3 VREF (EXTERNAL) M INTERNAL BUS U VDD X CMOD.7 CMOD.6 1/2R R R M U X 1/2R VREF (INTERNAL) CMOD.5 0 CMOD.3 CMOD.2 CMOD.1 CMOD.0 8
+ -
COMPARISON RESULT REGISTER (CMPREG)
4
Figure 12-1. Comparator Circuit Diagram
12-2
KS57C0502/C0504/P0504 MICROCONTROLLER
COMPARATOR
COMPARATOR MODE REGISTER (CMOD) The comparator mode register CMOD is an 8-bit register that is used to set the operation mode of the comparator. It is mapped to addresses FD6H-FD7H and can be manipulated using 8-bit memory instructions. Based on the CMOD.5 bit setting, an internal or an external reference voltage is input for the comparator, as follows: When CMOD.5 is set to logic zero: -- A reference voltage is selected by the CMOD.0 to CMOD.3 bit settings. -- P2.0 to P2.3 are used as analog input pins. -- The internal digital to analog converter generates 16 reference voltages. -- The comparator can detect 150 mV difference between the reference voltage and the analog input voltages. -- Comparator results are written into 4-bit comparison result register (CMPREG). When CMOD.5 is set to logic one: -- An external reference voltage is supplied from P2.3/CIN3. -- P2.0 to P2.2 are used as the analog input pins. -- The comparator can detect 150 mV difference between the reference voltage and the analog input voltages. -- Bits 0-2 in the CMPREG register contain the results; the content of bit 3 is not used. Bit 6 in the CMOD register controls conversion time while bit 7 enables or disables comparator operation to reduce power consumption. A RESET signal clears all bits to logic zero, causing the comparator operation to enter stop mode.
CMOD.7 CMOD.6 CMOD.5
0
CMOD.3 CMOD.2 CMOD.1 CMOD.0
FD6H-FD7H
Reference voltage (VREF) selection: VDD x (n + 0.5)/16, n = 0 to 15 1: CIN3; external reference, CIN0-2; analog input 0: Internal reference, CIN0-3; analog input
4 1: Conversion time (4 x 2 /fx, 15.2 s @4.19MHz) 7 0: Conversion time (4 x 2 /fx, 121.6 s @4.19MHz)
1: Comparator operation enable 0: Comparator operation disable
Figure 12-2. Comparator Mode Register Organization
12-3
COMPARATOR
KS57C0502/C0504/P0504 MICROCONTROLLER
PORT 2 MODE REGISTER (P2MOD) P2MOD register settings determine if port 2 is used for analog or digital input. The P2MOD register is 4-bit write only register. P2MOD is mapped to address FE2H and initialized to logic zero by a RESET, which configures port 2 as an analog input port. FE2H P2MOD.3 P2MOD.2 P2MOD.1 P2MOD.0
When bit is set to "1", the corresponding pin is configured as a digital input pin. When set to "0", configured as an analog input pin: P2MOD.0 for P2.0, P2MOD.1 for P2.1, P2MOD.2 for P2.2, and P2MOD.3 for P2.3. COMPARATOR OPERATION The comparator compars analog voltage input at CIN0-CIN3 with an external or internal reference voltage (VREF) that is selected by CMOD register. The result is written to the comparison result register CMPREG at address FD4H. The comparison result is calculated as follows. If "1" Analog input voltage VREF + 150 mV If "0" Analog input voltage VREF - 150 mV To obtain a comparison result, the data must be read out from the CMPREG register after VREF is updated by changing the CMOD value after a conversion time has elapsed.
ANALOG INPUT VOLTAGE (CIN0-3) REFERENCE VOLTAGE (VREF) COMPARISON TIME (CMPCLK x 4) COMPARATOR CLOCK (CMPCLK, fx/16, fx/128)
COMPARISON START COMPARISON RESULT (CMPREG) UNKNOWN
COMPARISON END
1
1
0
Figure 12-3. Conversion Characteristics
12-4
KS57C0502/C0504/P0504 MICROCONTROLLER
COMPARATOR
+ PROGRAMMING TIP -- Programming the Comparator
The following code converts the analog voltage input at CIN0-CIN2 pins into 4-bit digital code. BITR LD LD LD WAIT LD LD INCS JR LD LD EMB A,#0H P2MOD,A EA,#8XH CMOD,EA A,#0H A WAIT A,CMPREG P4,A
; ; ;
Analog input selection (CIN0-CIN3) x = 0-F, comparator enable Internal reference, conversion time (121.6 s)
; ;
Read the result Output the result from port 4
12-5
COMPARATOR
KS57C0502/C0504/P0504 MICROCONTROLLER
NOTES
12-6
KS57C0502/C0504/P0504 MICROCONTROLLER
SERIAL I/O INTERFACE
13
OVERVIEW
SERIAL I/O INTERFACE
The serial I/O interface (SIO) has the following functional components: -- 8-bit mode register (SMOD) -- Clock selector circuit -- 8-bit buffer register (SBUF) -- 3-bit serial clock counter Using the serial I/O interface, you can exchange 8-bit data with an external device. You control the transmission frequency by the appropriate bit settings to the SMOD register. The serial interface can run off an internal or an external clock source, or the TOL0 signal that is generated by the 8-bit timer/counter 0, TC0. If you use the TOL0 clock signal, you can modify its frequency to adjust the serial data transmission rate.
13-1
SERIAL I/O INTERFACE
KS57C0502/C0504/P0504 MICROCONTROLLER
SIO OPERATION SEQUENCE The general sequence of operations for the serial I/O interface may be summarized as follows: 1. Set SIO mode to transmit-and-receive or to receive-only. 2. Select MSB-first or LSB-first transmission mode. 3. Set the SCK clock signal in the mode register, SMOD. 4. Set SIO interrupt enable flag (IES) to "1". 5. Initiate SIO transmission by setting bit 3 of the SMOD to "1". 6. When the SIO operation is complete, IRQS flag is set and an interrupt is generated.
INTERNAL BUS 8 LSB or MSB first SO SI SBUF (8-BIT)
R Q
SCK
CLK D CLK
IRQS CLOCK SELECTOR
TOL0 fx/210 fx/2
R S
Q CLK
Q0 Q1 Q2 3-BIT COUNTER CLEAR
SMOD.7
SMOD.6 SMOD.5
- 8
SMOD.3 SMOD.2
SMOD.1
SMOD.0
Figure 13-1. Serial I/O Interface Circuit Diagram
13-2
KS57C0502/C0504/P0504 MICROCONTROLLER
SERIAL I/O INTERFACE
SERIAL I/O MODE REGISTER (SMOD) The serial I/O mode register, SMOD, is an 8-bit register that specifies the operation mode of the serial interface. SMOD is mapped to RAM address FE0H-FE1H and its reset value is logic zero. SMOD is organized in two 4-bit registers, as follows: FE0H FE1H SMOD.3 SMOD.7 SMOD.2 SMOD.6 SMOD.1 SMOD.5 SMOD.0 0
SMOD register settings enable you to select either MSB-first or LSB-first serial transmission, and to operate in transmit-and-receive mode or receive-only mode. SMOD is a write-only register and can be addressed only by 8-bit RAM control instructions. One exception to this is SMOD.3, which can be written by a 1-bit RAM control instruction. When SMOD.3 is set to 1, the contents of the serial interface interrupt request flag, IRQS, and the 3-bit serial clock counter are cleared, and SIO operations are initiated. When the SIO transmission starts, SMOD.3 is cleared to logic zero. Table 13-1. SIO Mode Register (SMOD) Organization SMOD.0 SMOD.1 SMOD.2 0 1 0 1 0 1 SMOD.3 SMOD.4 SMOD.7 0 1 0 SMOD.6 0 Most significant bit (MSB) is transmitted first Least significant bit (LSB) is transmitted first Receive-only mode; output buffer is off Transmit-and-receive mode Disable the data shifter and clock counter; retain contents of IRQS flag when serial transmission is halted Enable the data shifter and clock counter; set IRQS flag to "1" when serial transmission is halted Clear IRQS flag and 3-bit clock counter to "0"; initiate transmission and then reset this bit to logic zero Bit not used; value is always "0" SMOD.5 0 Clock Selection External clock at SCK pin R/W Status of SBUF SBUF is enabled when SIO operation is halted or when SCK goes high. Enable SBUF read/write SBUF is enabled when SIO operation is halted or when SCK goes high.
0 0 1
0 1 0
1 x 0
Use TOL0 clock from TC0 CPU clock: fx/4, fx/8, fx/64 4.09 kHz clock: fx/210
1
1
1
262 kHz clock: fx/24
NOTES: 1. 'fx' = system clock; 'x' means 'don't care.' 2. kHz frequency ratings assume a system clock (fx) running at 4.19 MHz. 3. The SIO clock selector circuit cannot select a fx/24 clock if the CPU clock is fx/64.
13-3
SERIAL I/O INTERFACE
KS57C0502/C0504/P0504 MICROCONTROLLER
SERIAL I/O TIMING DIAGRAMS
SCK
SI
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
IRQS SET SMOD.3
TRANSMIT COMPLETE
Figure 13-2. SIO Timing in Transmit/Receive Mode
SCK
SI
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO
HIGH IMPEDANCE
IRQS SET SMOD.3
TRANSMIT COMPLETE
Figure 13-3. SIO Timing in Receive-Only Mode
13-4
KS57C0502/C0504/P0504 MICROCONTROLLER
SERIAL I/O INTERFACE
SERIAL I/O BUFFER REGISTER (SBUF) When the serial interface operates in transmit-and-receive mode (SMOD.1 = "1"), transmit data in the SIO buffer register are output to the SO pin (P0.1) at the rate of one bit for each falling edge of the SIO clock. Receive data is simultaneously input from the SI pin (P0.2) to SBUF at the rate of one bit for each rising edge of the SIO clock. When receive-only mode is used, incoming data is input to the SIO buffer at the rate of one bit for each rising edge of the SIO clock. SBUF can be read or written using 8-bit RAM control instructions. It is mapped to addresses FE4H-FE5H. Following a RESET, the value of SBUF is undetermined.
+ PROGRAMMING TIP -- Setting Transmit/Receive Modes for Serial I/O
1. and Transmit the data value 48H through the serial I/O interface using an internal clock frequency of fx/24 in MSB-first mode: BITS SMB LD LD LD LD LD LD EMB 15 EA,#03H PMG1,EA EA,#48H SBUF,EA EA,#0EEH SMOD,EA
; ; ; ;
P0.0 / SCK and P0.1 / SO Output
SIO data transfer
SCK / P0.0
EXTERNAL DEVICE
SO / P0.1
2. Use CPU clock to transfer and receive serial data at high speed: BITS SMB LD LD LD LD LD LD BITR BTSTZ JR LD SMB LD EMB 15 EA,#03H PMG1,EA EA,TDATA SBUF,EA EA,#4FH SMOD,EA IES IRQS STEST EA,SBUF 0 RDATA,EA
;
P0.0 / SCK and P0.1 / SO Output, P0.2 / SI Input
;
SIO start
STEST
13-5
SERIAL I/O INTERFACE
KS57C0502/C0504/P0504 MICROCONTROLLER
+ PROGRAMMING TIP -- Setting Transmit/Receive Modes for Serial I/O (Continued)
3. Transmit and receive an internal clock frequency of 4.09 kHz (at 4.19 MHz) in LSB-first mode: BITS SMB LD LD LD LD LD LD EI BITS INTS PUSH PUSH LD SMB XCH SMB LD BITS POP POP IRET EMB 15 EA,#03H PMG1,EA EA,TDATA SBUF,EA EA,#8FH SMOD,EA IES * * SB EA EA,TDATA 15 EA,SBUF 0 RDATA,EA SMOD.3 EA SB
;
P0.0 / SCK and P0.1 / SO Output, P0.2/SI Input
;
SIO start
; ; ; ; ; ;
Store SMB, SRB Store EA EA Transmit data EA Receive data RDATA Receive data SIO start
SCK / P0.0
EXTERNAL DEVICE
SO / P0.1 SI / P0.2
13-6
KS57C0502/C0504/P0504 MICROCONTROLLER
SERIAL I/O INTERFACE
+ PROGRAMMING TIP -- Setting Transmit/Receive Modes for Serial I/O (Continued)
4. Transmit and receive an external clock in LSB-first mode: BITS SMB LD LD LD LD LD LD EI BITS INTS PUSH PUSH LD SMB XCH SMB LD BITS POP POP IRET EMB 15 EA,#02H PMG1,EA EA,TDATA SBUF,EA EA,#0FH SMOD,EA IES * * SB EA EA,TDATA 15 EA,SBUF 0 RDATA,EA SMOD.3 EA SB
;
P0.1 / SO Output, P0.0 / SCK and P0.2 / SI Input
;
SIO start
; ; ; ; ; ;
Store SMB, SRB Store EA EA Transmit data EA Receive data RDATA Receive data SIO start
SCK / P0.0
EXTERNAL DEVICE
SO / P0.1 SI / P0.2
High Speed SIO Transmission
13-7
SERIAL I/O INTERFACE
KS57C0502/C0504/P0504 MICROCONTROLLER
+ PROGRAMMING TIP -- Setting Transmit/Receive Modes for Serial I/O (Concluded)
Use CPU clock to transfer and receive serial data at high speed: BITS SMB LD LD LD LD LD LD BITR BTSTZ JR LD SMB LD EMB 15 EA,#03H PMG1,EA EA,TDATA SBUF,EA EA,#4FH SMOD,EA IES IRQS STEST EA,SBUF 0 RDATA,EA
;
P0.0 / SCK and P0.1 / SO Output, P0.2 / SI Input
;
SIO start
STEST
13-8
KS57C0502/C0504/P0504 MICROCONTROLLER
ELECTRICAL DATA
14
(TA = 25 C) Input Voltage
ELECTRICAL DATA
Table 14-1. Absolute Maximum Ratings
Parameter Supply Voltage
Symbol VDD VI VO IOH IOL
Conditions - All I/O ports - One I/O port active All I/O ports active
Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 -5 - 15 5 30 + 100
Units V V V mA
Output Voltage Output Current High
Output Current Low
Ports 0, 3, and 6 Ports 4 and 5 All ports, total
mA
Operating Temperature Storage Temperature
TA Tstg
- -
- 40 to + 85 - 65 to + 150
C C
Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage VOH Conditions Ports 4 and 5 Ports 0, 1, 2, 3, 6, and RESET Xin and Xout Ports 4 and 5 Ports 0, 1, 2, 3, 6, and RESET Xin and Xout VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 0, 3, 4, 5, 6 VDD - 1.0 - Min 0.7VDD 0.8VDD VDD - 0.1 - Typ - - - - Max VDD VDD VDD 0.3VDD 0.2VDD 0.1 - V V Units V
14-1
ELECTRICAL DATA
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Output Low Voltage Symbol VOL Conditions VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 4, 5 VDD = 4.5V to 5.5 V IOL = 4.0mA All output pins except Ports 4, 5 Input High Leakage Current ILIH1 VIN = VDD All input pins except Xin and Xout VIN = VDD Xin and Xout VIN = 0 V All input pins except Xin, Xout and
RESET
Min -
Typ -
Max 2
Units V
-
2
-
-
3
A
ILIH2 Input Low Leakage Current ILIL1
20 - - -3 A
ILIL2 Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILOH
VIN = 0 V Xin and Xout VO = VDD All output pins VO = 0 V - -
- 20 3 A
ILOL
-
-
-3
A
RL1
VI = 0 V; VDD = 5 V Port 0, 1, 3, 4, 5, 6 VDD = 3 V VDD = 5 V; VI = 0 V; RESET VDD = 3 V
25 50 100 200
50 100 250 500
100 200 400 800
k
RL2
14-2
KS57C0502/C0504/P0504 MICROCONTROLLER
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 Conditions Run mode; VDD = 5.0 V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10% IDD2 Idle mode; VDD = 5.0 V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10% IDD3 Stop mode; VDD = 5.0 V 10% Stop mode; VDD = 3.0 V 10% 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz - - Min - Typ 3.0 2.0 1.3 1.0 0.8 0.6 0.6 0.4 0.5 0.3 Max 8.0 5.5 4.0 3.0 2.5 1.8 1.5 1.0 3.0 2.0 A mA Units mA
NOTES: 1. D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up registers, output port drive currents and comparator. 2. The supply current assumes a CPU clock of fx/4.
Main Osc. Freq. ( Divided by 4 ) CPU CLOCK 1.5 MHz 6 MHz
1.05 MHz
4.2 MHz
15.625 kHz 1 2
2.7
400 kHz 3 4 5 6 7
SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-1. Standard Operating Voltage Range
14-3
ELECTRICAL DATA
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 14-3. Oscillators Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration
Xin Xout
Parameter
Test Condition
Min 0.4
Typ -
Max 6.0
Units MHz
Oscillation frequency (1) VDD = 2.7 V to 5.5 V
C1
C2
VDD = 1.8 V to 5.5 V Stabilization time (2) Crystal Oscillator
Xin Xout
0.4 - 0.4
- - -
4.2 4 6.0 ms MHz
VDD = 3.0 V
Oscillation frequency (1) VDD = 2.7 V to 5.5 V
C1
C2
VDD = 1.8 V to 5.5 V Stabilization time (2) External Clock
Xin Xout
0.4 - 0.4
- - -
4.2 10 6.0 ms MHz
VDD = 3.0 V VDD = 2.7 V to 5.5 V
Xin input frequency (1)
VDD = 1.8 V to 5.5 V Xin input high and low level width (tXH, tXL) -
0.4 83.3
- -
4.2 1250 ns
NOTES: 1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
14-4
KS57C0502/C0504/P0504 MICROCONTROLLER
ELECTRICAL DATA
Table 14-4. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - Typ - Max 15 15 15 Units pF pF pF
Table 14-5. Comparator Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.0 V to 5.5V, VSS = 0 V) Parameter Input Voltage Range Reference Voltage Range Input Voltage Accuracy Input Leakage Current Symbol - VREF VCIN ICIN, IREF Condition - - - - Min 0 0 - -3 Typ - - - - Max VDD VDD 150 3 Units V V mV A
Table 14-6. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time TCL0 Input Frequency TCL0 Input High, Low Width
SCK Cycle Time
Symbol tCY
Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V
Min 0.67 0.95 0
Typ -
Max 64
Units s
f TI
VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V
-
1.5 1
MHz MHz s
tTIH, tTIL
VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V
0.48 1.8 800 670 3200 3800
-
-
tKCY
VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source
-
-
ns
14-5
ELECTRICAL DATA
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 14-6. A.C. Electrical Characteristics ( Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter
SCK High, Low
Symbol tKH, tKL
Conditions VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source
Min 335 tKCY/2 - 50 1600 tKCY/2 - 150 100 150 150 500 400 400 600 500 -
Typ -
Max -
Units ns
Width
SI Setup Time to SCK High
tSIK
VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source
-
-
ns
SI Hold Time to SCK High
tKSI
VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source
-
-
ns
Output Delay for SCK to SO
tKSO (1)
VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source
-
300 250 1000 1000
ns
Interrupt Input High, Low Width
tINTH, tINTL tRSL
INT0 INT1, KS0 - KS2
(2)
-
-
s
10 10 - - s
RESET Input Low
Input
Width
NOTES: 1. R(1Kohm) and C (100pF) are the load resistance and load capacitance of the SO output line. 2. Minimum value for INT0 is based on a clock of 2tCY or 128 / fx as assigned by the IMOD0 register setting.
14-6
KS57C0502/C0504/P0504 MICROCONTROLLER
ELECTRICAL DATA
Table 14-7. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 1.8 V - Released by RESET Released by interrupt Min 1.8 - 0 - - Typ - 0.1 - 217 / fx
(2)
Max 5.5 10 - - -
Unit V A s ms ms
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator startup. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
TIMING WAVEFORMS
INTERNAL RESET OPERATION STOP MODE DATA RETENTION MODE IDLE MODE OPERATING MODE
VDD
EXECUTION OF STOP INSTRUCTION
RESET
VDDDR
tWAIT tSREL
Figure 14-2. Stop Mode Release Timing When Initiated By RESET
14-7
ELECTRICAL DATA
KS57C0502/C0504/P0504 MICROCONTROLLER
IDLE MODE STOP MODE DATA RETENTION MODE NORMAL OPERATING MODE
VDD VDDDR
EXECUTION OF STOP INSTRUCTION
tSREL
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST)
Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request
0.8 VDD 0.2 VDD MEASUREMENT POINTS
0.8 VDD
0.2 VDD
Figure 14-4. A.C. Timing Measurement Points (Except for Xin)
1 / fx
tXL
tXH
Xin
VDD - 0.2 V 0.2 V
Figure 14-5. Clock Timing Measurement at Xin
14-8
KS57C0502/C0504/P0504 MICROCONTROLLER
ELECTRICAL DATA
1 / fTI
tTIL
TCL
tTIH 0.8 VDD 0.2 VDD
Figure 14-6. TCL Timing
tRSL
RESET
0.2 VDD
Figure 14-7. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1 KS0 to KS2
0.8 VDD 0.2 VDD
Figure 14-8. Input Timing for External Interrupts
14-9
ELECTRICAL DATA
KS57C0502/C0504/P0504 MICROCONTROLLER
tCKY tKL
SCK
tKH
0.8 VDD 0.2 VDD
tSIK
tKSI
0.8 VDD
SI
INPUT DATA 0.2 VDD
tKSO
SO OUTPUT DATA
Figure 14-9. Serial Data Transfer Timing
14-10
KS57C0502/0504/P0504 MICROCONTROLLER
MECHANICAL DATA
15
MECHANICAL DATA
This section contains the following information about the device package: -- Package dimensions in millimeters -- Pad diagram -- Pad/pin coordinate data table
30 8.94 0.2
16
0 ~ 15
30-SDIP-400
#1
15
0.25 +0.1 - 0.0 5
3.81 0.2
(1.30)
0.56 0.1
1.12 0.1
1.778
NOTE: Typical dimensions are in millimeters.
Figure 15-1. 30-SDIP-400 Package Dimensions
3.30 0.3
0.51MIN
5.08MAX
27.48 0.2
10.16
15-1
MECHANICAL DATA
KS57C0502/0504/P0504 MICROCONTROLLER
15-2
KS57C0502/C0504/P0504 MICROCONTROLLER
KS57P0504 OTP
16
OVERVIEW
KS57P0504 OTP
The KS57P0504 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS57C0502/C0504 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The KS57P0504 is fully compatible with the KS57C0502/C0504, both in function and in pin configuration. Because of its simple programming requirements, the KS57P0504 is ideal for use as an evaluation chip for the KS57C0502/C0504.
VSS / VSS Xout Xin TEST / TEST P1.0 / INT0 P1.1 / INT1
RESET
/ RESET P0.0 / SCK
P0.1 / SO P0.2 / SI P2.0 / CIN0 P2.1 / CIN1 P2.2 / CIN2 P2.3 / CIN3 P3.0 / TCL0
1 30 2 29 3 28 4 27 5 26 6 25 7 24 8 KS57P0504 23 (30-SDIP) 9 22 10 21 11 20 12 19 13 18 14 17 15 16
VDD / VDD P6.3 / BUZ / SCLK P6.2 / KS2 / SDAT P6.1 / KS1 P6.0 / KS0 P5.3 P5.2 P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 P3.2 / CLO P3.1 / TCLO0
NOTE: The bolds indicate an OTP pin name.
Figure 16-1. KS57P0504 Pin Assignments (30-SDIP Package)
16-1
KS57P0504 OTP
KS57C0502/C0504/P0504 MICROCONTROLLER
VSS / VSS Xout Xin TEST / TEST P1.0 / INT0 P1.1 / INT1
RESET / RESET
NC P0.0 /SCK P0.1 / SO P0.2 / SI P2.0 / CIN0 P2.1 / CIN1 P2.2 / CIN2 P2.3 / CIN3 P3.0 / TCL0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
KS57P0504
(32-SOP)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD / VDD P6.3 / BUZ /SCLK P6.2 / KS2 /SDAT P6.1 / KS1 P6.0 / KS0 P5.3 P5.2 P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 NC P3.2 / CLO P3.1 / TCLO0
NOTE: The bolds indicate an OTP pin name.
Figure 16-2. KS57P0504 Pin Assignments (32-SOP Package)
16-2
KS57C0502/C0504/P0504 MICROCONTROLLER
KS57P0504 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P6.2 Pin Name SDAT Pin No. 28 (30) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming.
P6.3 TEST
SCLK VPP(TEST)
29 (31) 4 (4)
I/O I
RESET
RESET
7 (7) 30/1 (32/1)
I I
VDD / VSS
VDD / VSS
NOTE: ( ) means the 32-SOP OTP pin number.
Table 16-2. Comparison of KS57P0504 and KS57C0502/C0504 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability KS57P0504 4 K-byte EPROM 2.0 V to 5.5 V VDD = 5 V, VPP(TEST)=12.5V 30 SDIP, 32 SOP User Program one time KS57C0502/C0504 2 K-byte mask ROM: KS57C0502 4 K-byte mask ROM: KS57C0504 1.8 V to 5.5V - 30 SDIP, 32 SOP Programmed at the factory
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the KS57P0504, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/ MEM 0 0 0 1 ADDRESS (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 MODE EPROM read EPROM program EPROM verify EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-3
KS57P0504 OTP
KS57C0502/C0504/P0504 MICROCONTROLLER
OTP ELECTRICAL DATA Table 16-4. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO IOH IOL All I/O ports - One I/O port active All I/O ports active Output Current Low Ports 0, 3, and 6 Ports 4 and 5 All ports, total Operating Temperature Storage Temperature TA Tstg - - Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 -5 - 15 5 30 + 100 - 40 to + 85 - 65 to + 150
C C
Units V V V mA
mA
Table 16-5. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage VOH Conditions Ports 4 and 5 Ports 0, 1, 2, 3, 6, and RESET Xin and Xout Ports 4 and 5 Ports 0, 1, 2, 3, 6, and RESET Xin and Xout VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 0, 3, 4, 5, 6 VDD - 1.0 - Min 0.7VDD 0.8VDD VDD - 0.1 - Typ - - - - Max VDD VDD VDD 0.3VDD 0.2VDD 0.1 - V V Units V
16-4
KS57C0502/C0504/P0504 MICROCONTROLLER
KS57P0504 OTP
Table 16-5. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Output Low Voltage Symbol VOL Conditions VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 4, 5 VDD = 4.5V to 5.5 V IOL = 4.0mA All output pins except Ports 4, 5 Input High Leakage Current ILIH1 VIN = VDD All input pins except Xin and Xout VIN = VDD Xin and Xout VIN = 0 V All input pins except Xin, Xout and
RESET
Min -
Typ -
Max 2
Units V
-
2
-
-
3
A
ILIH2 Input Low Leakage Current ILIL1
20 - - -3 A
ILIL2 Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILOH
VIN = 0 V Xin and Xout VO = VDD All output pins VO = 0 V - -
- 20 3 A
ILOL
-
-
-3
A
RL1
VI = 0 V; VDD = 5 V Port 0, 1, 3, 4, 5, 6 VDD = 3 V VDD = 5 V; VI = 0 V; RESET VDD = 3 V
25 50 100 200
50 100 250 500
100 200 400 800
k
RL2
16-5
KS57P0504 OTP
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 16-5. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 Conditions Run mode; VDD = 5.0 V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10% IDD2 Idle mode; VDD = 5.0 V 10% Crystal oscillator; C1=C2=22pF VDD = 3 V 10% IDD3 Stop mode; VDD = 5.0 V 10% Stop mode; VDD = 3.0 V 10% 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz - - Min - Typ 3.0 2.0 1.3 1.0 0.8 0.6 0.6 0.4 0.5 0.3 Max 8.0 5.5 4.0 3.0 2.5 1.8 1.5 1.0 3.0 2.0 A mA Units mA
NOTES: 1. D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up registers, 2. output port drive currents and comparator. The supply current assumes a CPU clock of fx/4.
Main Osc. Freq. ( Divided by 4 ) CPU CLOCK 1.5 MHz 6 MHz
1.05 MHz
4.2 MHz
15.625 kHz 1 2
2.7
400 kHz 3 4 5 6 7
SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16-3. Standard Operating Voltage Range
16-6
KS57C0502/C0504/P0504 MICROCONTROLLER
KS57P0504 OTP
Table 16-6. Oscillators Characteristics (TA = - 40 C + 85 C, VDD = 2.0 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration
Xin Xout
Parameter
Test Condition
Min 0.4
Typ -
Max 6.0
Units MHz
Oscillation frequency (1) VDD = 2.7 V to 5.5 V
C1
C2
VDD = 2.0 V to 5.5 V Stabilization time (2) Crystal Oscillator
Xin Xout
0.4 - 0.4
- - -
4.2 4 6.0 ms MHz
VDD = 3.0 V
Oscillation frequency (1) VDD = 2.7 V to 5.5 V
C1
C2
VDD = 2.0 V to 5.5 V Stabilization time (2) External Clock
Xin Xout
0.4 - 0.4
- - -
4.2 10 6.0 ms MHz
VDD = 3.0 V VDD = 2.7 V to 5.5 V
Xin input frequency (1)
VDD = 2.0 V to 5.5 V Xin input high and low level width (tXH, tXL) -
0.4 83.3
- -
4.2 1250 ns
NOTES: 1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
16-7
KS57P0504 OTP
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 16-7. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - Typ - Max 15 15 15 Units pF pF pF
Table 16-8. Comparator Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.0 V to 5.5V, VSS = 0 V) Parameter Input Voltage Range Reference Voltage Range Input Voltage Accuracy Input Leakage Current Symbol - VREF VCIN ICIN, IREF Condition - - - - Min 0 0 - -3 Typ - - - - Max VDD VDD 150 3 Units V V mV A
Table 16-9. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Instruction Cycle Time Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V TCL0 Input Frequency f TI VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V TCL0 Input High, Low Width tTIH, tTIL VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V
SCK Cycle Time
Min 0.67 0.95 0
Typ -
Max 64
Units s
-
1.5 1
MHz MHz s
0.48 1.8 800 670 3200 3800
-
-
tKCY
VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source
-
-
ns
16-8
KS57C0502/C0504/P0504 MICROCONTROLLER
KS57P0504 OTP
Table 16-9. A.C. Electrical Characteristics ( Concluded) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter
SCK High, Low
Symbol tKH, tKL
Conditions VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source
Min 335 tKCY/2 - 50 1600 tKCY/2 - 150 100 150 150 500 400 400 600 500 -
Typ -
Max -
Units ns
Width
SI Setup Time to SCK High
tSIK
VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source
-
-
ns
SI Hold Time to SCK High
tKSI
VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source
-
-
ns
Output Delay for SCK to SO
tKSO (1)
VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source
-
300 250 1000 1000
ns
Interrupt Input High, Low Width
tINTH, tINTL tRSL
INT0 INT1, KS0 - KS2
(2)
-
-
s
10 10 - - s
RESET Input Low
Input
Width
NOTES: 1. R(1Kohm) and C (100pF) are the load resistance and load capacitance of the SO output line. 2. Minimum value for INT0 is based on a clock of 2tCY or 128 / fx as assigned by the IMOD0 register setting.
16-9
KS57P0504 OTP
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 16-10. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 2.0 V - Released by RESET Released by interrupt Min 2.0 - 0 - - Typ - 0.1 - 217 / fx
(2)
Max 5.5 10 - - -
Unit V A s ms ms
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
16-10
KS57C0502/C0504/P0504 MICROCONTROLLER
KS57P0504 OTP
START
Address= First Location
VDD =5V, V PP=12.5V
x=0
Program One 1ms Pulse
Increment X
YES
x = 10
NO FAIL
Verify Byte
Verify 1 Byte
FAIL
Last Address
NO
Increment Address
VDD = VPP= 5 V
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 16-4. OTP Programming Algorithm
16-11
KS57P0504 OTP
KS57C0502/C0504/P0504 MICROCONTROLLER
NOTES
16-12
KS57C0502/C0504/P0504 MICROCONTROLLER
DEVELOPMENT TOOLS
17
OVERVIEW SHINE
Development Tools
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for KS57, KS86, KS88 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options.
Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. SASM57 The SASM57 is an relocatable assembler for Samsung's KS57-series microcontrollers. The SASM57 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM57 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by HEX2ROM, the value 'FF' is filled into the unused ROM area upto the maximum ROM size of the target device automatically. TARGET BOARDS Target boards are available for all KS57-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. OTPs One time programmable microcontroller (OTP) for the KS57C0502/C0504 microcontroller and OTP programmer (Gang) are now available.
17-1
DEVELOPMENT TOOLS
KS57C0502/C0504/P0504 MICROCONTROLLER
IBM-PC AT or Compatible
RS-232C
SMDS2+
PROM/MTP WRITER UNIT
TARGET APPLICATION SYSTEM
RAM BREAK/ DISPLAY UNIT PROBE ADAPTER BUS TRACE/TIMER UNIT
POD SAM4 BASE UNIT
TB570502A/0504A TARGET BOARD
POWER SUPPLY UNIT
EVA CHIP
Figure 17-1. SMDS Product Configuration (SMDS2+)
17-2
KS57C0502/C0504/P0504 MICROCONTROLLER
DEVELOPMENT TOOLS
TB570502A/0504A TARGET BOARD The TB570502A/0504A target board is used for the KS57C0502/C0504/P0504 microcontroller. It is supported by the SMDS2+ development system.
TB570502A/0504A
To User_Vcc OFF ON
RESET IDLE 74HC11 STOP
+
+
25 100-PIN CONNECTOR J101
1 1
XI
30
EXTERNAL TRIGGERS CH1 CH2
MDS
XTAL
15
30-PIN CONNECTOR
16
100 QFP KS57E0500 EVA CHIP
1
30
SM1253A
Figure 17-2. TB570502A/TB570504A Target Board Configuration
17-3
DEVELOPMENT TOOLS
KS57C0502/C0504/P0504 MICROCONTROLLER
Table 17-1. Power Selection Settings for TB570502A/TB570504A 'To User_Vcc' Settings To User_Vcc OFF ON Operating Mode Comments The SMDS2/SMDS2+ supplies VCC to the target board (evaluation chip) and the target system.
TB570502A /0504A
VCC VSS
TARGET SYSTEM
VCC SMDS2/SMDS2+
To User_Vcc OFF ON
TB570502A /0504A External VCC VSS VCC SMDS2/SMDS2+ TARGET SYSTEM
The SMDS2/SMDS2+ supplies VCC only to the target board (evaluation chip). The target system must have its own power supply.
Table 17-2. Clock Selection Settings for TB570502A/TB570504A Sub Clock Setting XTI MDS XTAL Operating Mode Comments Set the XTI switch to "MDS" when the target board is connected to the SMDS2/SMDS2+.
EVA CHIP KS57E 0500 XTOUT No connection 100 pin connector
XTIN
SMDS2/SMDS2+
XTI MDS XTAL
EVA CHIP KS57E0500 XTOUT XTAL TARGET BOARD
Set the XTI switch to "XTAL" when the target board is used as a standalone unit, and is not connected to the SMDS2/SMDS2+.
XTIN
17-4
KS57C0502/C0504/P0504 MICROCONTROLLER
DEVELOPMENT TOOLS
Table 17-3. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments Connector from external trigger sources of the application system
EXTERNAL TRIGGERS CH1 CH2
You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace functions. IDLE LED This LED is ON when the evaluation chip (KS57E0500) is in idle mode. STOP LED This LED is ON when the evaluation chip (KS57E0500) is in stop mode.
17-5
DEVELOPMENT TOOLS
KS57C0502/C0504/P0504 MICROCONTROLLER
J101
VSS Xout Xin TEST P1.0/INT0 P1.1/INT1
RESET
P0.0/ SCK P0.1/SO P0.2/SI P2.0/CIN0 P2.1/CIN1 P2.2/CIN2 P2.3/CIN3 P3.0/TCL0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDD P6.3/BUZ/SCLK P6.2/KS2/SDAT P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 P3.2/CLO P3.1/TCLO0
Figure 17-3. 30-Pin Connector for TB570502A/TB570504A
30-PIN DIP CONNECTOR
TARGET BOARD J101 1 30 30-PIN DIP CONNECTOR
TARGET SYSTEM
1
30
Target Cable for 32-SDIP Socket Part Name: AP30SD-C Order Code: SM6519
15 16 15 16
Figure 17-4. TB570502A/TB570504A Adapter Cable for 30-SDIP Package (KS57C0502/C0504/P0504)
17-6

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